AssemblerOpt (Jikes RVM API)

java.lang.Object
- org.jikesrvm.compilers.common.assembler.AbstractAssembler
- - org.jikesrvm.compilers.common.assembler.ia32.Assembler
  - - org.jikesrvm.compilers.opt.mir2mc.ia32.AssemblerBase
    - - org.jikesrvm.compilers.opt.mir2mc.ia32.AssemblerOpt

```
public class AssemblerOpt
extends AssemblerBase
```
This class is the automatically-generated assembler for the optimizing compiler. It consists of methods that understand the possible operand combinations of each instruction type, and how to translate those operands to calls to the Assember low-level emit method It is generated by GenerateAssembler.java

Field Summary

Fields
Modifier and Type Field and Description

private int instructionCount
The number of instructions emitted so far
- Fields inherited from class org.jikesrvm.compilers.opt.mir2mc.ia32.AssemblerBase
  ir, mcOffsets
- Fields inherited from class org.jikesrvm.compilers.common.assembler.ia32.Assembler
  forwardRefs, lister, mi

Fields
Modifier and Type	Field and Description
`private int`	`instructionCount` The number of instructions emitted so far

Constructor Summary

Constructors
Constructor and Description

AssemblerOpt(int bcSize, boolean print, IR ir)

Constructors
Constructor and Description
`AssemblerOpt(int bcSize, boolean print, IR ir)`

Method Summary

All Methods Instance Methods Concrete Methods
Modifier and Type	Method and Description
`private void`	`doADC(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ADC operator
`private void`	`doADD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ADD operator
`private void`	`doADDSD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ADDSD operator
`private void`	`doADDSS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ADDSS operator
`private void`	`doAND(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a AND operator
`private void`	`doANDNPD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ANDNPD operator
`private void`	`doANDNPS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ANDNPS operator
`private void`	`doANDPD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ANDPD operator
`private void`	`doANDPS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ANDPS operator
`private void`	`doBSWAP(Instruction inst)` Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a BSWAP operator
`private void`	`doBT(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Test instruction and has a BT operator
`private void`	`doBTC(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Test instruction and has a BTC operator
`private void`	`doBTR(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Test instruction and has a BTR operator
`private void`	`doBTS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Test instruction and has a BTS operator
`private void`	`doCALL(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Call instruction and has a CALL operator
`private void`	`doCDO(Instruction inst)` Emit the given instruction, assuming that it is a MIR_ConvertDW2QW instruction and has a CDO operator
`private void`	`doCDQ(Instruction inst)` Emit the given instruction, assuming that it is a MIR_ConvertDW2QW instruction and has a CDQ operator
`private void`	`doCDQE(Instruction inst)` Emit the given instruction, assuming that it is a MIR_ConvertDW2QW instruction and has a CDQE operator
`private void`	`doCMOV(Instruction inst)` Emit the given instruction, assuming that it is a MIR_CondMove instruction and has a CMOV operator
`private void`	`doCMP(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Compare instruction and has a CMP operator
`private void`	`doCMPEQSD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPEQSD operator
`private void`	`doCMPEQSS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPEQSS operator
`private void`	`doCMPLESD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPLESD operator
`private void`	`doCMPLESS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPLESS operator
`private void`	`doCMPLTSD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPLTSD operator
`private void`	`doCMPLTSS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPLTSS operator
`private void`	`doCMPNESD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNESD operator
`private void`	`doCMPNESS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNESS operator
`private void`	`doCMPNLESD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNLESD operator
`private void`	`doCMPNLESS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNLESS operator
`private void`	`doCMPNLTSD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNLTSD operator
`private void`	`doCMPNLTSS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNLTSS operator
`private void`	`doCMPORDSD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPORDSD operator
`private void`	`doCMPORDSS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPORDSS operator
`private void`	`doCMPUNORDSD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPUNORDSD operator
`private void`	`doCMPUNORDSS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPUNORDSS operator
`private void`	`doCMPXCHG(Instruction inst)` Emit the given instruction, assuming that it is a MIR_CompareExchange instruction and has a CMPXCHG operator
`private void`	`doCMPXCHG8B(Instruction inst)` Emit the given instruction, assuming that it is a MIR_CompareExchange8B instruction and has a CMPXCHG8B operator
`private void`	`doCVTSD2SI(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSD2SI operator
`private void`	`doCVTSD2SIQ(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSD2SIQ operator
`private void`	`doCVTSD2SS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSD2SS operator
`private void`	`doCVTSI2SD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSI2SD operator
`private void`	`doCVTSI2SDQ(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSI2SDQ operator
`private void`	`doCVTSI2SS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSI2SS operator
`private void`	`doCVTSS2SD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSS2SD operator
`private void`	`doCVTSS2SI(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSS2SI operator
`private void`	`doCVTTSD2SI(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTTSD2SI operator
`private void`	`doCVTTSD2SIQ(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTTSD2SIQ operator
`private void`	`doCVTTSS2SI(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTTSS2SI operator
`private void`	`doDEC(Instruction inst)` Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a DEC operator
`private void`	`doDIV(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Divide instruction and has a DIV operator
`private void`	`doDIVSD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a DIVSD operator
`private void`	`doDIVSS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a DIVSS operator
`private void`	`doFADD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FADD operator
`private void`	`doFADDP(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FADDP operator
`private void`	`doFCHS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a FCHS operator
`private void`	`doFCMOV(Instruction inst)` Emit the given instruction, assuming that it is a MIR_CondMove instruction and has a FCMOV operator
`private void`	`doFCOMI(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Compare instruction and has a FCOMI operator
`private void`	`doFCOMIP(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Compare instruction and has a FCOMIP operator
`private void`	`doFDIV(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FDIV operator
`private void`	`doFDIVP(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FDIVP operator
`private void`	`doFDIVR(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FDIVR operator
`private void`	`doFDIVRP(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FDIVRP operator
`private void`	`doFFREE(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FFREE operator
`private void`	`doFFREEP(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FFREEP operator
`private void`	`doFIADD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FIADD operator
`private void`	`doFIDIV(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FIDIV operator
`private void`	`doFIDIVR(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FIDIVR operator
`private void`	`doFILD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a FILD operator
`private void`	`doFIMUL(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FIMUL operator
`private void`	`doFINIT(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Empty instruction and has a FINIT operator
`private void`	`doFIST(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a FIST operator
`private void`	`doFISTP(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a FISTP operator
`private void`	`doFISUB(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FISUB operator
`private void`	`doFISUBR(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FISUBR operator
`private void`	`doFLD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a FLD operator
`private void`	`doFLD1(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLD1 operator
`private void`	`doFLDCW(Instruction inst)` Emit the given instruction, assuming that it is a MIR_UnaryNoRes instruction and has a FLDCW operator
`private void`	`doFLDL2E(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDL2E operator
`private void`	`doFLDL2T(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDL2T operator
`private void`	`doFLDLG2(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDLG2 operator
`private void`	`doFLDLN2(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDLN2 operator
`private void`	`doFLDPI(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDPI operator
`private void`	`doFLDZ(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDZ operator
`private void`	`doFMUL(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FMUL operator
`private void`	`doFMULP(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FMULP operator
`private void`	`doFNINIT(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Empty instruction and has a FNINIT operator
`private void`	`doFNSAVE(Instruction inst)` Emit the given instruction, assuming that it is a MIR_FSave instruction and has a FNSAVE operator
`private void`	`doFNSTCW(Instruction inst)` Emit the given instruction, assuming that it is a MIR_UnaryNoRes instruction and has a FNSTCW operator
`private void`	`doFPREM(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FPREM operator
`private void`	`doFRSTOR(Instruction inst)` Emit the given instruction, assuming that it is a MIR_FSave instruction and has a FRSTOR operator
`private void`	`doFST(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a FST operator
`private void`	`doFSTCW(Instruction inst)` Emit the given instruction, assuming that it is a MIR_UnaryNoRes instruction and has a FSTCW operator
`private void`	`doFSTP(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a FSTP operator
`private void`	`doFSTSW(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a FSTSW operator
`private void`	`doFSUB(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FSUB operator
`private void`	`doFSUBP(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FSUBP operator
`private void`	`doFSUBR(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FSUBR operator
`private void`	`doFSUBRP(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FSUBRP operator
`private void`	`doFUCOMI(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Compare instruction and has a FUCOMI operator
`private void`	`doFUCOMIP(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Compare instruction and has a FUCOMIP operator
`private void`	`doFXCH(Instruction inst)` Emit the given instruction, assuming that it is a MIR_XChng instruction and has a FXCH operator
`private void`	`doIDIV(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Divide instruction and has a IDIV operator
`private void`	`doIMUL1(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Multiply instruction and has a IMUL1 operator
`private void`	`doIMUL2(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a IMUL2 operator
`private void`	`doINC(Instruction inst)` Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a INC operator
`void`	`doInst(Instruction inst)` Assembles the given instruction.
`private void`	`doINT(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Trap instruction and has a INT operator
`private void`	`doLEA(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Lea instruction and has a LEA operator
`private void`	`doMETHODSTART(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a METHODSTART operator
`private void`	`doMFENCE(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Empty instruction and has a MFENCE operator
`private void`	`doMOV(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOV operator
`private void`	`doMOVAPD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVAPD operator
`private void`	`doMOVAPS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVAPS operator
`private void`	`doMOVD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVD operator
`private void`	`doMOVLPD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVLPD operator
`private void`	`doMOVLPS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVLPS operator
`private void`	`doMOVQ(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVQ operator
`private void`	`doMOVSD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVSD operator
`private void`	`doMOVSS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVSS operator
`private void`	`doMOVSX(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a MOVSX operator
`private void`	`doMOVSXDQ(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a MOVSXDQ operator
`private void`	`doMOVSXQ(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a MOVSXQ operator
`private void`	`doMOVZX(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a MOVZX operator
`private void`	`doMOVZXQ(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a MOVZXQ operator
`private void`	`doMUL(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Multiply instruction and has a MUL operator
`private void`	`doMULSD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a MULSD operator
`private void`	`doMULSS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a MULSS operator
`private void`	`doNEG(Instruction inst)` Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a NEG operator
`private void`	`doNOT(Instruction inst)` Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a NOT operator
`private void`	`doOFFSET(Instruction inst)` Emit the given instruction, assuming that it is a MIR_CaseLabel instruction and has a OFFSET operator
`private void`	`doOR(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a OR operator
`private void`	`doORPD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ORPD operator
`private void`	`doORPS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ORPS operator
`private void`	`doPAUSE(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Empty instruction and has a PAUSE operator
`private void`	`doPOP(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a POP operator
`private void`	`doPREFETCHNTA(Instruction inst)` Emit the given instruction, assuming that it is a MIR_CacheOp instruction and has a PREFETCHNTA operator
`private void`	`doPSLLQ(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a PSLLQ operator
`private void`	`doPSRLQ(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a PSRLQ operator
`private void`	`doPUSH(Instruction inst)` Emit the given instruction, assuming that it is a MIR_UnaryNoRes instruction and has a PUSH operator
`private void`	`doRCL(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a RCL operator
`private void`	`doRCR(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a RCR operator
`private void`	`doRDTSC(Instruction inst)` Emit the given instruction, assuming that it is a MIR_RDTSC instruction and has a RDTSC operator
`private void`	`doRET(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Return instruction and has a RET operator
`private void`	`doROL(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ROL operator
`private void`	`doROR(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ROR operator
`private void`	`doSAL(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SAL operator
`private void`	`doSAR(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SAR operator
`private void`	`doSBB(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SBB operator
`private void`	`doSET(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Set instruction and has a SET operator
`private void`	`doSHL(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SHL operator
`private void`	`doSHLD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_DoubleShift instruction and has a SHLD operator
`private void`	`doSHR(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SHR operator
`private void`	`doSHRD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_DoubleShift instruction and has a SHRD operator
`private void`	`doSQRTSD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a SQRTSD operator
`private void`	`doSQRTSS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Unary instruction and has a SQRTSS operator
`private void`	`doSUB(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SUB operator
`private void`	`doSUBSD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SUBSD operator
`private void`	`doSUBSS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SUBSS operator
`private void`	`doTEST(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Test instruction and has a TEST operator
`private void`	`doUCOMISD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Compare instruction and has a UCOMISD operator
`private void`	`doUCOMISS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_Compare instruction and has a UCOMISS operator
`private void`	`doXOR(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a XOR operator
`private void`	`doXORPD(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a XORPD operator
`private void`	`doXORPS(Instruction inst)` Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a XORPS operator

Methods inherited from class org.jikesrvm.compilers.opt.mir2mc.ia32.AssemblerBase
disasm, doIMMQ_MOV, doJCC, doJMP, doLOWTABLESWITCH, estimateSize, generateCode, getBase, getCond, getDisp, getFPR_Reg, getGPR_Reg, getImm, getImmQuad, getIndex, getLabel, getMM_Reg, getReg, getScale, getXMM_Reg, isAbs, isByte, isCond, isFPR_Reg, isGPR_Reg, isHotCode, isImm, isImmOrLabel, isLabel, isMM_Reg, isQuad, isReg, isRegDisp, isRegIdx, isRegInd, isRegOff, isWord, isXMM_Reg, targetIsClose

Methods inherited from class org.jikesrvm.compilers.common.assembler.ia32.Assembler
baselineEmitLoadTIB, comment, emitADC_Abs_Imm_Byte, emitADC_Abs_Imm_Quad, emitADC_Abs_Imm_Word, emitADC_Abs_Imm, emitADC_Abs_Reg_Byte, emitADC_Abs_Reg_Quad, emitADC_Abs_Reg_Word, emitADC_Abs_Reg, emitADC_Reg_Abs_Byte, emitADC_Reg_Abs_Quad, emitADC_Reg_Abs_Word, emitADC_Reg_Abs, emitADC_Reg_Imm_Byte, emitADC_Reg_Imm_Quad, emitADC_Reg_Imm_Word, emitADC_Reg_Imm, emitADC_Reg_Reg_Byte, emitADC_Reg_Reg_Quad, emitADC_Reg_Reg_Word, emitADC_Reg_Reg, emitADC_Reg_RegDisp_Byte, emitADC_Reg_RegDisp_Quad, emitADC_Reg_RegDisp_Word, emitADC_Reg_RegDisp, emitADC_Reg_RegIdx_Byte, emitADC_Reg_RegIdx_Quad, emitADC_Reg_RegIdx_Word, emitADC_Reg_RegIdx, emitADC_Reg_RegInd_Byte, emitADC_Reg_RegInd_Quad, emitADC_Reg_RegInd_Word, emitADC_Reg_RegInd, emitADC_Reg_RegOff_Byte, emitADC_Reg_RegOff_Quad, emitADC_Reg_RegOff_Word, emitADC_Reg_RegOff, emitADC_RegDisp_Imm_Byte, emitADC_RegDisp_Imm_Quad, emitADC_RegDisp_Imm_Word, emitADC_RegDisp_Imm, emitADC_RegDisp_Reg_Byte, emitADC_RegDisp_Reg_Quad, emitADC_RegDisp_Reg_Word, emitADC_RegDisp_Reg, emitADC_RegIdx_Imm_Byte, emitADC_RegIdx_Imm_Quad, emitADC_RegIdx_Imm_Word, emitADC_RegIdx_Imm, emitADC_RegIdx_Reg_Byte, emitADC_RegIdx_Reg_Quad, emitADC_RegIdx_Reg_Word, emitADC_RegIdx_Reg, emitADC_RegInd_Imm_Byte, emitADC_RegInd_Imm_Quad, emitADC_RegInd_Imm_Word, emitADC_RegInd_Imm, emitADC_RegInd_Reg_Byte, emitADC_RegInd_Reg_Quad, emitADC_RegInd_Reg_Word, emitADC_RegInd_Reg, emitADC_RegOff_Imm_Byte, emitADC_RegOff_Imm_Quad, emitADC_RegOff_Imm_Word, emitADC_RegOff_Imm, emitADC_RegOff_Reg_Byte, emitADC_RegOff_Reg_Quad, emitADC_RegOff_Reg_Word, emitADC_RegOff_Reg, emitADD_Abs_Imm_Byte, emitADD_Abs_Imm_Quad, emitADD_Abs_Imm_Word, emitADD_Abs_Imm, emitADD_Abs_Reg_Byte, emitADD_Abs_Reg_Quad, emitADD_Abs_Reg_Word, emitADD_Abs_Reg, emitADD_Reg_Abs_Byte, emitADD_Reg_Abs_Quad, emitADD_Reg_Abs_Word, emitADD_Reg_Abs, emitADD_Reg_Imm_Byte, emitADD_Reg_Imm_Quad, emitADD_Reg_Imm_Word, emitADD_Reg_Imm, emitADD_Reg_Reg_Byte, emitADD_Reg_Reg_Quad, emitADD_Reg_Reg_Word, emitADD_Reg_Reg, emitADD_Reg_RegDisp_Byte, emitADD_Reg_RegDisp_Quad, emitADD_Reg_RegDisp_Word, emitADD_Reg_RegDisp, emitADD_Reg_RegIdx_Byte, emitADD_Reg_RegIdx_Quad, emitADD_Reg_RegIdx_Word, emitADD_Reg_RegIdx, emitADD_Reg_RegInd_Byte, emitADD_Reg_RegInd_Quad, emitADD_Reg_RegInd_Word, emitADD_Reg_RegInd, emitADD_Reg_RegOff_Byte, emitADD_Reg_RegOff_Quad, emitADD_Reg_RegOff_Word, emitADD_Reg_RegOff, emitADD_RegDisp_Imm_Byte, emitADD_RegDisp_Imm_Quad, emitADD_RegDisp_Imm_Word, emitADD_RegDisp_Imm, emitADD_RegDisp_Reg_Byte, emitADD_RegDisp_Reg_Quad, emitADD_RegDisp_Reg_Word, emitADD_RegDisp_Reg, emitADD_RegIdx_Imm_Byte, emitADD_RegIdx_Imm_Quad, emitADD_RegIdx_Imm_Word, emitADD_RegIdx_Imm, emitADD_RegIdx_Reg_Byte, emitADD_RegIdx_Reg_Quad, emitADD_RegIdx_Reg_Word, emitADD_RegIdx_Reg, emitADD_RegInd_Imm_Byte, emitADD_RegInd_Imm_Quad, emitADD_RegInd_Imm_Word, emitADD_RegInd_Imm, emitADD_RegInd_Reg_Byte, emitADD_RegInd_Reg_Quad, emitADD_RegInd_Reg_Word, emitADD_RegInd_Reg, emitADD_RegOff_Imm_Byte, emitADD_RegOff_Imm_Quad, emitADD_RegOff_Imm_Word, emitADD_RegOff_Imm, emitADD_RegOff_Reg_Byte, emitADD_RegOff_Reg_Quad, emitADD_RegOff_Reg_Word, emitADD_RegOff_Reg, emitADDSD_Reg_Abs, emitADDSD_Reg_Reg, emitADDSD_Reg_RegDisp, emitADDSD_Reg_RegIdx, emitADDSD_Reg_RegInd, emitADDSD_Reg_RegOff, emitADDSS_Reg_Abs, emitADDSS_Reg_Reg, emitADDSS_Reg_RegDisp, emitADDSS_Reg_RegIdx, emitADDSS_Reg_RegInd, emitADDSS_Reg_RegOff, emitAND_Abs_Imm_Byte, emitAND_Abs_Imm_Quad, emitAND_Abs_Imm_Word, emitAND_Abs_Imm, emitAND_Abs_Reg_Byte, emitAND_Abs_Reg_Quad, emitAND_Abs_Reg_Word, emitAND_Abs_Reg, emitAND_Reg_Abs_Byte, emitAND_Reg_Abs_Quad, emitAND_Reg_Abs_Word, emitAND_Reg_Abs, emitAND_Reg_Imm_Byte, emitAND_Reg_Imm_Quad, emitAND_Reg_Imm_Word, emitAND_Reg_Imm, emitAND_Reg_Reg_Byte, emitAND_Reg_Reg_Quad, emitAND_Reg_Reg_Word, emitAND_Reg_Reg, emitAND_Reg_RegDisp_Byte, emitAND_Reg_RegDisp_Quad, emitAND_Reg_RegDisp_Word, emitAND_Reg_RegDisp, emitAND_Reg_RegIdx_Byte, emitAND_Reg_RegIdx_Quad, emitAND_Reg_RegIdx_Word, emitAND_Reg_RegIdx, emitAND_Reg_RegInd_Byte, emitAND_Reg_RegInd_Quad, emitAND_Reg_RegInd_Word, emitAND_Reg_RegInd, emitAND_Reg_RegOff_Byte, emitAND_Reg_RegOff_Quad, emitAND_Reg_RegOff_Word, emitAND_Reg_RegOff, emitAND_RegDisp_Imm_Byte, emitAND_RegDisp_Imm_Quad, emitAND_RegDisp_Imm_Word, emitAND_RegDisp_Imm, emitAND_RegDisp_Reg_Byte, emitAND_RegDisp_Reg_Quad, emitAND_RegDisp_Reg_Word, emitAND_RegDisp_Reg, emitAND_RegIdx_Imm_Byte, emitAND_RegIdx_Imm_Quad, emitAND_RegIdx_Imm_Word, emitAND_RegIdx_Imm, emitAND_RegIdx_Reg_Byte, emitAND_RegIdx_Reg_Quad, emitAND_RegIdx_Reg_Word, emitAND_RegIdx_Reg, emitAND_RegInd_Imm_Byte, emitAND_RegInd_Imm_Quad, emitAND_RegInd_Imm_Word, emitAND_RegInd_Imm, emitAND_RegInd_Reg_Byte, emitAND_RegInd_Reg_Quad, emitAND_RegInd_Reg_Word, emitAND_RegInd_Reg, emitAND_RegOff_Imm_Byte, emitAND_RegOff_Imm_Quad, emitAND_RegOff_Imm_Word, emitAND_RegOff_Imm, emitAND_RegOff_Reg_Byte, emitAND_RegOff_Reg_Quad, emitAND_RegOff_Reg_Word, emitAND_RegOff_Reg, emitANDNPD_Reg_Abs, emitANDNPD_Reg_Reg, emitANDNPD_Reg_RegDisp, emitANDNPD_Reg_RegIdx, emitANDNPD_Reg_RegInd, emitANDNPD_Reg_RegOff, emitANDNPS_Reg_Abs, emitANDNPS_Reg_Reg, emitANDNPS_Reg_RegDisp, emitANDNPS_Reg_RegIdx, emitANDNPS_Reg_RegInd, emitANDNPS_Reg_RegOff, emitANDPD_Reg_Abs, emitANDPD_Reg_Reg, emitANDPD_Reg_RegDisp, emitANDPD_Reg_RegIdx, emitANDPD_Reg_RegInd, emitANDPD_Reg_RegOff, emitANDPS_Reg_Abs, emitANDPS_Reg_Reg, emitANDPS_Reg_RegDisp, emitANDPS_Reg_RegIdx, emitANDPS_Reg_RegInd, emitANDPS_Reg_RegOff, emitBranchLikelyNextInstruction, emitBranchUnlikelyNextInstruction, emitBSWAP_Reg_Quad, emitBSWAP_Reg, emitBT_Abs_Imm_Quad, emitBT_Abs_Imm, emitBT_Abs_Reg_Quad, emitBT_Abs_Reg, emitBT_Reg_Imm_Quad, emitBT_Reg_Imm, emitBT_Reg_Reg_Quad, emitBT_Reg_Reg, emitBT_RegDisp_Imm_Quad, emitBT_RegDisp_Imm, emitBT_RegDisp_Reg_Quad, emitBT_RegDisp_Reg, emitBT_RegIdx_Imm_Quad, emitBT_RegIdx_Imm, emitBT_RegIdx_Reg_Quad, emitBT_RegIdx_Reg, emitBT_RegInd_Imm_Quad, emitBT_RegInd_Imm, emitBT_RegInd_Reg_Quad, emitBT_RegInd_Reg, emitBT_RegOff_Imm_Quad, emitBT_RegOff_Imm, emitBT_RegOff_Reg_Quad, emitBT_RegOff_Reg, emitBTC_Abs_Imm_Quad, emitBTC_Abs_Imm, emitBTC_Abs_Reg_Quad, emitBTC_Abs_Reg, emitBTC_Reg_Imm_Quad, emitBTC_Reg_Imm, emitBTC_Reg_Reg_Quad, emitBTC_Reg_Reg, emitBTC_RegDisp_Imm_Quad, emitBTC_RegDisp_Imm, emitBTC_RegDisp_Reg_Quad, emitBTC_RegDisp_Reg, emitBTC_RegIdx_Imm_Quad, emitBTC_RegIdx_Imm, emitBTC_RegIdx_Reg_Quad, emitBTC_RegIdx_Reg, emitBTC_RegInd_Imm_Quad, emitBTC_RegInd_Imm, emitBTC_RegInd_Reg_Quad, emitBTC_RegInd_Reg, emitBTC_RegOff_Imm_Quad, emitBTC_RegOff_Imm, emitBTC_RegOff_Reg_Quad, emitBTC_RegOff_Reg, emitBTR_Abs_Imm_Quad, emitBTR_Abs_Imm, emitBTR_Abs_Reg_Quad, emitBTR_Abs_Reg, emitBTR_Reg_Imm_Quad, emitBTR_Reg_Imm, emitBTR_Reg_Reg_Quad, emitBTR_Reg_Reg, emitBTR_RegDisp_Imm_Quad, emitBTR_RegDisp_Imm, emitBTR_RegDisp_Reg_Quad, emitBTR_RegDisp_Reg, emitBTR_RegIdx_Imm_Quad, emitBTR_RegIdx_Imm, emitBTR_RegIdx_Reg_Quad, emitBTR_RegIdx_Reg, emitBTR_RegInd_Imm_Quad, emitBTR_RegInd_Imm, emitBTR_RegInd_Reg_Quad, emitBTR_RegInd_Reg, emitBTR_RegOff_Imm_Quad, emitBTR_RegOff_Imm, emitBTR_RegOff_Reg_Quad, emitBTR_RegOff_Reg, emitBTS_Abs_Imm_Quad, emitBTS_Abs_Imm, emitBTS_Abs_Reg_Quad, emitBTS_Abs_Reg, emitBTS_Reg_Imm_Quad, emitBTS_Reg_Imm, emitBTS_Reg_Reg_Quad, emitBTS_Reg_Reg, emitBTS_RegDisp_Imm_Quad, emitBTS_RegDisp_Imm, emitBTS_RegDisp_Reg_Quad, emitBTS_RegDisp_Reg, emitBTS_RegIdx_Imm_Quad, emitBTS_RegIdx_Imm, emitBTS_RegIdx_Reg_Quad, emitBTS_RegIdx_Reg, emitBTS_RegInd_Imm_Quad, emitBTS_RegInd_Imm, emitBTS_RegInd_Reg_Quad, emitBTS_RegInd_Reg, emitBTS_RegOff_Imm_Quad, emitBTS_RegOff_Imm, emitBTS_RegOff_Reg_Quad, emitBTS_RegOff_Reg, emitCALL_Abs, emitCALL_Imm, emitCALL_ImmOrLabel, emitCALL_Label, emitCALL_Reg, emitCALL_RegDisp, emitCALL_RegIdx, emitCALL_RegInd, emitCALL_RegOff, emitCDO, emitCDQ, emitCDQE, emitCMOV_Cond_Reg_Abs, emitCMOV_Cond_Reg_Reg, emitCMOV_Cond_Reg_RegDisp, emitCMOV_Cond_Reg_RegIdx, emitCMOV_Cond_Reg_RegInd, emitCMOV_Cond_Reg_RegOff, emitCMP_Abs_Imm_Byte, emitCMP_Abs_Imm_Quad, emitCMP_Abs_Imm_Word, emitCMP_Abs_Imm, emitCMP_Abs_Reg_Byte, emitCMP_Abs_Reg_Quad, emitCMP_Abs_Reg_Word, emitCMP_Abs_Reg, emitCMP_Reg_Abs_Byte, emitCMP_Reg_Abs_Quad, emitCMP_Reg_Abs_Word, emitCMP_Reg_Abs, emitCMP_Reg_Imm_Byte, emitCMP_Reg_Imm_Quad, emitCMP_Reg_Imm_Word, emitCMP_Reg_Imm, emitCMP_Reg_Reg_Byte, emitCMP_Reg_Reg_Quad, emitCMP_Reg_Reg_Word, emitCMP_Reg_Reg, emitCMP_Reg_RegDisp_Byte, emitCMP_Reg_RegDisp_Quad, emitCMP_Reg_RegDisp_Word, emitCMP_Reg_RegDisp, emitCMP_Reg_RegIdx_Byte, emitCMP_Reg_RegIdx_Quad, emitCMP_Reg_RegIdx_Word, emitCMP_Reg_RegIdx, emitCMP_Reg_RegInd_Byte, emitCMP_Reg_RegInd_Quad, emitCMP_Reg_RegInd_Word, emitCMP_Reg_RegInd, emitCMP_Reg_RegOff_Byte, emitCMP_Reg_RegOff_Quad, emitCMP_Reg_RegOff_Word, emitCMP_Reg_RegOff, emitCMP_RegDisp_Imm_Byte, emitCMP_RegDisp_Imm_Quad, emitCMP_RegDisp_Imm_Word, emitCMP_RegDisp_Imm, emitCMP_RegDisp_Reg_Byte, emitCMP_RegDisp_Reg_Quad, emitCMP_RegDisp_Reg_Word, emitCMP_RegDisp_Reg, emitCMP_RegIdx_Imm_Byte, emitCMP_RegIdx_Imm_Quad, emitCMP_RegIdx_Imm_Word, emitCMP_RegIdx_Imm, emitCMP_RegIdx_Reg_Byte, emitCMP_RegIdx_Reg_Quad, emitCMP_RegIdx_Reg_Word, emitCMP_RegIdx_Reg, emitCMP_RegInd_Imm_Byte, emitCMP_RegInd_Imm_Quad, emitCMP_RegInd_Imm_Word, emitCMP_RegInd_Imm, emitCMP_RegInd_Reg_Byte, emitCMP_RegInd_Reg_Quad, emitCMP_RegInd_Reg_Word, emitCMP_RegInd_Reg, emitCMP_RegOff_Imm_Byte, emitCMP_RegOff_Imm_Quad, emitCMP_RegOff_Imm_Word, emitCMP_RegOff_Imm, emitCMP_RegOff_Reg_Byte, emitCMP_RegOff_Reg_Quad, emitCMP_RegOff_Reg_Word, emitCMP_RegOff_Reg, emitCMPEQSD_Reg_Abs, emitCMPEQSD_Reg_Reg, emitCMPEQSD_Reg_RegDisp, emitCMPEQSD_Reg_RegIdx, emitCMPEQSD_Reg_RegInd, emitCMPEQSD_Reg_RegOff, emitCMPEQSS_Reg_Abs, emitCMPEQSS_Reg_Reg, emitCMPEQSS_Reg_RegDisp, emitCMPEQSS_Reg_RegIdx, emitCMPEQSS_Reg_RegInd, emitCMPEQSS_Reg_RegOff, emitCMPLESD_Reg_Abs, emitCMPLESD_Reg_Reg, emitCMPLESD_Reg_RegDisp, emitCMPLESD_Reg_RegIdx, emitCMPLESD_Reg_RegInd, emitCMPLESD_Reg_RegOff, emitCMPLESS_Reg_Abs, emitCMPLESS_Reg_Reg, emitCMPLESS_Reg_RegDisp, emitCMPLESS_Reg_RegIdx, emitCMPLESS_Reg_RegInd, emitCMPLESS_Reg_RegOff, emitCMPLTSD_Reg_Abs, emitCMPLTSD_Reg_Reg, emitCMPLTSD_Reg_RegDisp, emitCMPLTSD_Reg_RegIdx, emitCMPLTSD_Reg_RegInd, emitCMPLTSD_Reg_RegOff, emitCMPLTSS_Reg_Abs, emitCMPLTSS_Reg_Reg, emitCMPLTSS_Reg_RegDisp, emitCMPLTSS_Reg_RegIdx, emitCMPLTSS_Reg_RegInd, emitCMPLTSS_Reg_RegOff, emitCMPNESD_Reg_Abs, emitCMPNESD_Reg_Reg, emitCMPNESD_Reg_RegDisp, emitCMPNESD_Reg_RegIdx, emitCMPNESD_Reg_RegInd, emitCMPNESD_Reg_RegOff, emitCMPNESS_Reg_Abs, emitCMPNESS_Reg_Reg, emitCMPNESS_Reg_RegDisp, emitCMPNESS_Reg_RegIdx, emitCMPNESS_Reg_RegInd, emitCMPNESS_Reg_RegOff, emitCMPNLESD_Reg_Abs, emitCMPNLESD_Reg_Reg, emitCMPNLESD_Reg_RegDisp, emitCMPNLESD_Reg_RegIdx, emitCMPNLESD_Reg_RegInd, emitCMPNLESD_Reg_RegOff, emitCMPNLESS_Reg_Abs, emitCMPNLESS_Reg_Reg, emitCMPNLESS_Reg_RegDisp, emitCMPNLESS_Reg_RegIdx, emitCMPNLESS_Reg_RegInd, emitCMPNLESS_Reg_RegOff, emitCMPNLTSD_Reg_Abs, emitCMPNLTSD_Reg_Reg, emitCMPNLTSD_Reg_RegDisp, emitCMPNLTSD_Reg_RegIdx, emitCMPNLTSD_Reg_RegInd, emitCMPNLTSD_Reg_RegOff, emitCMPNLTSS_Reg_Abs, emitCMPNLTSS_Reg_Reg, emitCMPNLTSS_Reg_RegDisp, emitCMPNLTSS_Reg_RegIdx, emitCMPNLTSS_Reg_RegInd, emitCMPNLTSS_Reg_RegOff, emitCMPORDSD_Reg_Abs, emitCMPORDSD_Reg_Reg, emitCMPORDSD_Reg_RegDisp, emitCMPORDSD_Reg_RegIdx, emitCMPORDSD_Reg_RegInd, emitCMPORDSD_Reg_RegOff, emitCMPORDSS_Reg_Abs, emitCMPORDSS_Reg_Reg, emitCMPORDSS_Reg_RegDisp, emitCMPORDSS_Reg_RegIdx, emitCMPORDSS_Reg_RegInd, emitCMPORDSS_Reg_RegOff, emitCMPUNORDSD_Reg_Abs, emitCMPUNORDSD_Reg_Reg, emitCMPUNORDSD_Reg_RegDisp, emitCMPUNORDSD_Reg_RegIdx, emitCMPUNORDSD_Reg_RegInd, emitCMPUNORDSD_Reg_RegOff, emitCMPUNORDSS_Reg_Abs, emitCMPUNORDSS_Reg_Reg, emitCMPUNORDSS_Reg_RegDisp, emitCMPUNORDSS_Reg_RegIdx, emitCMPUNORDSS_Reg_RegInd, emitCMPUNORDSS_Reg_RegOff, emitCMPXCHG_Abs_Reg_Quad, emitCMPXCHG_Abs_Reg, emitCMPXCHG_Reg_Reg_Quad, emitCMPXCHG_Reg_Reg, emitCMPXCHG_RegDisp_Reg_Quad, emitCMPXCHG_RegDisp_Reg, emitCMPXCHG_RegIdx_Reg_Quad, emitCMPXCHG_RegIdx_Reg, emitCMPXCHG_RegInd_Reg_Quad, emitCMPXCHG_RegInd_Reg, emitCMPXCHG_RegOff_Reg_Quad, emitCMPXCHG_RegOff_Reg, emitCMPXCHG8B_Abs, emitCMPXCHG8B_RegDisp, emitCMPXCHG8B_RegIdx, emitCMPXCHG8B_RegInd, emitCMPXCHG8B_RegOff, emitCVTSD2SI_Reg_Abs, emitCVTSD2SI_Reg_Reg, emitCVTSD2SI_Reg_RegDisp, emitCVTSD2SI_Reg_RegIdx, emitCVTSD2SI_Reg_RegInd, emitCVTSD2SI_Reg_RegOff, emitCVTSD2SIQ_Reg_Abs_Quad, emitCVTSD2SIQ_Reg_Reg_Quad, emitCVTSD2SIQ_Reg_RegDisp_Quad, emitCVTSD2SIQ_Reg_RegIdx_Quad, emitCVTSD2SIQ_Reg_RegInd_Quad, emitCVTSD2SIQ_Reg_RegOff_Quad, emitCVTSD2SS_Reg_Abs, emitCVTSD2SS_Reg_Reg, emitCVTSD2SS_Reg_RegDisp, emitCVTSD2SS_Reg_RegIdx, emitCVTSD2SS_Reg_RegInd, emitCVTSD2SS_Reg_RegOff, emitCVTSI2SD_Reg_Abs, emitCVTSI2SD_Reg_Reg, emitCVTSI2SD_Reg_RegDisp, emitCVTSI2SD_Reg_RegIdx, emitCVTSI2SD_Reg_RegInd, emitCVTSI2SD_Reg_RegOff, emitCVTSI2SDQ_Reg_Abs_Quad, emitCVTSI2SDQ_Reg_Reg_Quad, emitCVTSI2SDQ_Reg_RegDisp_Quad, emitCVTSI2SDQ_Reg_RegIdx_Quad, emitCVTSI2SDQ_Reg_RegInd_Quad, emitCVTSI2SDQ_Reg_RegOff_Quad, emitCVTSI2SS_Reg_Abs_Quad, emitCVTSI2SS_Reg_Abs, emitCVTSI2SS_Reg_Reg_Quad, emitCVTSI2SS_Reg_Reg, emitCVTSI2SS_Reg_RegDisp_Quad, emitCVTSI2SS_Reg_RegDisp, emitCVTSI2SS_Reg_RegIdx_Quad, emitCVTSI2SS_Reg_RegIdx, emitCVTSI2SS_Reg_RegInd_Quad, emitCVTSI2SS_Reg_RegInd, emitCVTSI2SS_Reg_RegOff_Quad, emitCVTSI2SS_Reg_RegOff, emitCVTSS2SD_Reg_Abs, emitCVTSS2SD_Reg_Reg, emitCVTSS2SD_Reg_RegDisp, emitCVTSS2SD_Reg_RegIdx, emitCVTSS2SD_Reg_RegInd, emitCVTSS2SD_Reg_RegOff, emitCVTSS2SI_Reg_Abs_Quad, emitCVTSS2SI_Reg_Abs, emitCVTSS2SI_Reg_Reg_Quad, emitCVTSS2SI_Reg_Reg, emitCVTSS2SI_Reg_RegDisp_Quad, emitCVTSS2SI_Reg_RegDisp, emitCVTSS2SI_Reg_RegIdx_Quad, emitCVTSS2SI_Reg_RegIdx, emitCVTSS2SI_Reg_RegInd_Quad, emitCVTSS2SI_Reg_RegInd, emitCVTSS2SI_Reg_RegOff_Quad, emitCVTSS2SI_Reg_RegOff, emitCVTTSD2SI_Reg_Abs, emitCVTTSD2SI_Reg_Reg, emitCVTTSD2SI_Reg_RegDisp, emitCVTTSD2SI_Reg_RegIdx, emitCVTTSD2SI_Reg_RegInd, emitCVTTSD2SI_Reg_RegOff, emitCVTTSD2SIQ_Reg_Abs_Quad, emitCVTTSD2SIQ_Reg_Reg_Quad, emitCVTTSD2SIQ_Reg_RegDisp_Quad, emitCVTTSD2SIQ_Reg_RegIdx_Quad, emitCVTTSD2SIQ_Reg_RegInd_Quad, emitCVTTSD2SIQ_Reg_RegOff_Quad, emitCVTTSS2SI_Reg_Abs_Quad, emitCVTTSS2SI_Reg_Abs, emitCVTTSS2SI_Reg_Reg_Quad, emitCVTTSS2SI_Reg_Reg, emitCVTTSS2SI_Reg_RegDisp_Quad, emitCVTTSS2SI_Reg_RegDisp, emitCVTTSS2SI_Reg_RegIdx_Quad, emitCVTTSS2SI_Reg_RegIdx, emitCVTTSS2SI_Reg_RegInd_Quad, emitCVTTSS2SI_Reg_RegInd, emitCVTTSS2SI_Reg_RegOff_Quad, emitCVTTSS2SI_Reg_RegOff, emitDEC_Abs_Byte, emitDEC_Abs_Quad, emitDEC_Abs_Word, emitDEC_Abs, emitDEC_Reg_Byte, emitDEC_Reg_Quad, emitDEC_Reg_Word, emitDEC_Reg, emitDEC_RegDisp_Byte, emitDEC_RegDisp_Quad, emitDEC_RegDisp_Word, emitDEC_RegDisp, emitDEC_RegIdx_Byte, emitDEC_RegIdx_Quad, emitDEC_RegIdx_Word, emitDEC_RegIdx, emitDEC_RegInd_Byte, emitDEC_RegInd_Quad, emitDEC_RegInd_Word, emitDEC_RegInd, emitDEC_RegOff_Byte, emitDEC_RegOff_Quad, emitDEC_RegOff_Word, emitDEC_RegOff, emitDIV_Reg_Abs_Quad, emitDIV_Reg_Abs, emitDIV_Reg_Reg_Quad, emitDIV_Reg_Reg, emitDIV_Reg_RegDisp_Quad, emitDIV_Reg_RegDisp, emitDIV_Reg_RegIdx_Quad, emitDIV_Reg_RegIdx, emitDIV_Reg_RegInd_Quad, emitDIV_Reg_RegInd, emitDIV_Reg_RegOff_Quad, emitDIV_Reg_RegOff, emitDIVSD_Reg_Abs, emitDIVSD_Reg_Reg, emitDIVSD_Reg_RegDisp, emitDIVSD_Reg_RegIdx, emitDIVSD_Reg_RegInd, emitDIVSD_Reg_RegOff, emitDIVSS_Reg_Abs, emitDIVSS_Reg_Reg, emitDIVSS_Reg_RegDisp, emitDIVSS_Reg_RegIdx, emitDIVSS_Reg_RegInd, emitDIVSS_Reg_RegOff, emitEMMS, emitENTER_Imm, emitFADD_Reg_Abs_Quad, emitFADD_Reg_Abs, emitFADD_Reg_Reg, emitFADD_Reg_RegDisp_Quad, emitFADD_Reg_RegDisp, emitFADD_Reg_RegIdx_Quad, emitFADD_Reg_RegIdx, emitFADD_Reg_RegInd_Quad, emitFADD_Reg_RegInd, emitFADD_Reg_RegOff_Quad, emitFADD_Reg_RegOff, emitFADDP_Reg_Reg, emitFCHS, emitFCMOV_Cond_Reg_Reg, emitFCOMI_Reg_Reg, emitFCOMIP_Reg_Reg, emitFDIV_Reg_Abs_Quad, emitFDIV_Reg_Abs, emitFDIV_Reg_Reg, emitFDIV_Reg_RegDisp_Quad, emitFDIV_Reg_RegDisp, emitFDIV_Reg_RegIdx_Quad, emitFDIV_Reg_RegIdx, emitFDIV_Reg_RegInd_Quad, emitFDIV_Reg_RegInd, emitFDIV_Reg_RegOff_Quad, emitFDIV_Reg_RegOff, emitFDIVP_Reg_Reg, emitFDIVR_Reg_Abs_Quad, emitFDIVR_Reg_Abs, emitFDIVR_Reg_Reg, emitFDIVR_Reg_RegDisp_Quad, emitFDIVR_Reg_RegDisp, emitFDIVR_Reg_RegIdx_Quad, emitFDIVR_Reg_RegIdx, emitFDIVR_Reg_RegInd_Quad, emitFDIVR_Reg_RegInd, emitFDIVR_Reg_RegOff_Quad, emitFDIVR_Reg_RegOff, emitFDIVRP_Reg_Reg, emitFFREE_Reg, emitFFREEP_Reg, emitFIADD_Reg_Abs_Word, emitFIADD_Reg_Abs, emitFIADD_Reg_RegDisp_Word, emitFIADD_Reg_RegDisp, emitFIADD_Reg_RegIdx_Word, emitFIADD_Reg_RegIdx, emitFIADD_Reg_RegInd_Word, emitFIADD_Reg_RegInd, emitFIADD_Reg_RegOff_Word, emitFIADD_Reg_RegOff, emitFIDIV_Reg_Abs_Word, emitFIDIV_Reg_Abs, emitFIDIV_Reg_RegDisp_Word, emitFIDIV_Reg_RegDisp, emitFIDIV_Reg_RegIdx_Word, emitFIDIV_Reg_RegIdx, emitFIDIV_Reg_RegInd_Word, emitFIDIV_Reg_RegInd, emitFIDIV_Reg_RegOff_Word, emitFIDIV_Reg_RegOff, emitFIDIVR_Reg_Abs_Word, emitFIDIVR_Reg_Abs, emitFIDIVR_Reg_RegDisp_Word, emitFIDIVR_Reg_RegDisp, emitFIDIVR_Reg_RegIdx_Word, emitFIDIVR_Reg_RegIdx, emitFIDIVR_Reg_RegInd_Word, emitFIDIVR_Reg_RegInd, emitFIDIVR_Reg_RegOff_Word, emitFIDIVR_Reg_RegOff, emitFILD_Reg_Abs_Quad, emitFILD_Reg_Abs_Word, emitFILD_Reg_Abs, emitFILD_Reg_RegDisp_Quad, emitFILD_Reg_RegDisp_Word, emitFILD_Reg_RegDisp, emitFILD_Reg_RegIdx_Quad, emitFILD_Reg_RegIdx_Word, emitFILD_Reg_RegIdx, emitFILD_Reg_RegInd_Quad, emitFILD_Reg_RegInd_Word, emitFILD_Reg_RegInd, emitFILD_Reg_RegOff_Quad, emitFILD_Reg_RegOff_Word, emitFILD_Reg_RegOff, emitFIMUL_Reg_Abs_Word, emitFIMUL_Reg_Abs, emitFIMUL_Reg_RegDisp_Word, emitFIMUL_Reg_RegDisp, emitFIMUL_Reg_RegIdx_Word, emitFIMUL_Reg_RegIdx, emitFIMUL_Reg_RegInd_Word, emitFIMUL_Reg_RegInd, emitFIMUL_Reg_RegOff_Word, emitFIMUL_Reg_RegOff, emitFINIT, emitFIST_Abs_Reg_Word, emitFIST_Abs_Reg, emitFIST_RegDisp_Reg_Word, emitFIST_RegDisp_Reg, emitFIST_RegIdx_Reg_Word, emitFIST_RegIdx_Reg, emitFIST_RegInd_Reg_Word, emitFIST_RegInd_Reg, emitFIST_RegOff_Reg_Word, emitFIST_RegOff_Reg, emitFISTP_Abs_Reg_Quad, emitFISTP_Abs_Reg_Word, emitFISTP_Abs_Reg, emitFISTP_RegDisp_Reg_Quad, emitFISTP_RegDisp_Reg_Word, emitFISTP_RegDisp_Reg, emitFISTP_RegIdx_Reg_Quad, emitFISTP_RegIdx_Reg_Word, emitFISTP_RegIdx_Reg, emitFISTP_RegInd_Reg_Quad, emitFISTP_RegInd_Reg_Word, emitFISTP_RegInd_Reg, emitFISTP_RegOff_Reg_Quad, emitFISTP_RegOff_Reg_Word, emitFISTP_RegOff_Reg, emitFISUB_Reg_Abs_Word, emitFISUB_Reg_Abs, emitFISUB_Reg_RegDisp_Word, emitFISUB_Reg_RegDisp, emitFISUB_Reg_RegIdx_Word, emitFISUB_Reg_RegIdx, emitFISUB_Reg_RegInd_Word, emitFISUB_Reg_RegInd, emitFISUB_Reg_RegOff_Word, emitFISUB_Reg_RegOff, emitFISUBR_Reg_Abs_Word, emitFISUBR_Reg_Abs, emitFISUBR_Reg_RegDisp_Word, emitFISUBR_Reg_RegDisp, emitFISUBR_Reg_RegIdx_Word, emitFISUBR_Reg_RegIdx, emitFISUBR_Reg_RegInd_Word, emitFISUBR_Reg_RegInd, emitFISUBR_Reg_RegOff_Word, emitFISUBR_Reg_RegOff, emitFLD_Reg_Abs_Quad, emitFLD_Reg_Abs, emitFLD_Reg_Reg, emitFLD_Reg_RegDisp_Quad, emitFLD_Reg_RegDisp, emitFLD_Reg_RegIdx_Quad, emitFLD_Reg_RegIdx, emitFLD_Reg_RegInd_Quad, emitFLD_Reg_RegInd, emitFLD_Reg_RegOff_Quad, emitFLD_Reg_RegOff, emitFLD1_Reg, emitFLDCW_Abs, emitFLDCW_RegDisp, emitFLDCW_RegIdx, emitFLDCW_RegInd, emitFLDCW_RegOff, emitFLDL2E_Reg, emitFLDL2T_Reg, emitFLDLG2_Reg, emitFLDLN2_Reg, emitFLDPI_Reg, emitFLDZ_Reg, emitFMUL_Reg_Abs_Quad, emitFMUL_Reg_Abs, emitFMUL_Reg_Reg, emitFMUL_Reg_RegDisp_Quad, emitFMUL_Reg_RegDisp, emitFMUL_Reg_RegIdx_Quad, emitFMUL_Reg_RegIdx, emitFMUL_Reg_RegInd_Quad, emitFMUL_Reg_RegInd, emitFMUL_Reg_RegOff_Quad, emitFMUL_Reg_RegOff, emitFMULP_Reg_Reg, emitFNINIT, emitFNSAVE_Abs, emitFNSAVE_RegDisp, emitFNSAVE_RegIdx, emitFNSAVE_RegInd, emitFNSAVE_RegOff, emitFNSTCW_Abs, emitFNSTCW_RegDisp, emitFNSTCW_RegIdx, emitFNSTCW_RegInd, emitFNSTCW_RegOff, emitFNSTSW_Abs, emitFNSTSW_Reg, emitFNSTSW_RegDisp, emitFNSTSW_RegIdx, emitFNSTSW_RegInd, emitFNSTSW_RegOff, emitFNSTSW, emitFPREM, emitFRSTOR_Abs, emitFRSTOR_RegDisp, emitFRSTOR_RegIdx, emitFRSTOR_RegInd, emitFRSTOR_RegOff, emitFSAVE_Abs, emitFSAVE_RegDisp, emitFSAVE_RegIdx, emitFSAVE_RegInd, emitFSAVE_RegOff, emitFST_Abs_Reg_Quad, emitFST_Abs_Reg, emitFST_Reg_Reg, emitFST_RegDisp_Reg_Quad, emitFST_RegDisp_Reg, emitFST_RegIdx_Reg_Quad, emitFST_RegIdx_Reg, emitFST_RegInd_Reg_Quad, emitFST_RegInd_Reg, emitFST_RegOff_Reg_Quad, emitFST_RegOff_Reg, emitFSTCW_Abs, emitFSTCW_RegDisp, emitFSTCW_RegIdx, emitFSTCW_RegInd, emitFSTCW_RegOff, emitFSTP_Abs_Reg_Quad, emitFSTP_Abs_Reg, emitFSTP_Reg_Reg, emitFSTP_RegDisp_Reg_Quad, emitFSTP_RegDisp_Reg, emitFSTP_RegIdx_Reg_Quad, emitFSTP_RegIdx_Reg, emitFSTP_RegInd_Reg_Quad, emitFSTP_RegInd_Reg, emitFSTP_RegOff_Reg_Quad, emitFSTP_RegOff_Reg, emitFSTSW_Abs, emitFSTSW_Reg, emitFSTSW_RegDisp, emitFSTSW_RegIdx, emitFSTSW_RegInd, emitFSTSW_RegOff, emitFSUB_Reg_Abs_Quad, emitFSUB_Reg_Abs, emitFSUB_Reg_Reg, emitFSUB_Reg_RegDisp_Quad, emitFSUB_Reg_RegDisp, emitFSUB_Reg_RegIdx_Quad, emitFSUB_Reg_RegIdx, emitFSUB_Reg_RegInd_Quad, emitFSUB_Reg_RegInd, emitFSUB_Reg_RegOff_Quad, emitFSUB_Reg_RegOff, emitFSUBP_Reg_Reg, emitFSUBR_Reg_Abs_Quad, emitFSUBR_Reg_Abs, emitFSUBR_Reg_Reg, emitFSUBR_Reg_RegDisp_Quad, emitFSUBR_Reg_RegDisp, emitFSUBR_Reg_RegIdx_Quad, emitFSUBR_Reg_RegIdx, emitFSUBR_Reg_RegInd_Quad, emitFSUBR_Reg_RegInd, emitFSUBR_Reg_RegOff_Quad, emitFSUBR_Reg_RegOff, emitFSUBRP_Reg_Reg, emitFUCOMI_Reg_Reg, emitFUCOMIP_Reg_Reg, emitFUCOMPP, emitFXCH_Reg_Reg, emitIDIV_Reg_Abs_Quad, emitIDIV_Reg_Abs, emitIDIV_Reg_Reg_Quad, emitIDIV_Reg_Reg, emitIDIV_Reg_RegDisp_Quad, emitIDIV_Reg_RegDisp, emitIDIV_Reg_RegIdx_Quad, emitIDIV_Reg_RegIdx, emitIDIV_Reg_RegInd_Quad, emitIDIV_Reg_RegInd, emitIDIV_Reg_RegOff_Quad, emitIDIV_Reg_RegOff, emitIMUL1_Reg_Abs_Quad, emitIMUL1_Reg_Abs, emitIMUL1_Reg_Reg_Quad, emitIMUL1_Reg_Reg, emitIMUL1_Reg_RegDisp_Quad, emitIMUL1_Reg_RegDisp, emitIMUL1_Reg_RegIdx_Quad, emitIMUL1_Reg_RegIdx, emitIMUL1_Reg_RegInd_Quad, emitIMUL1_Reg_RegInd, emitIMUL1_Reg_RegOff_Quad, emitIMUL1_Reg_RegOff, emitIMUL2_Reg_Abs_Quad, emitIMUL2_Reg_Abs, emitIMUL2_Reg_Imm_Quad, emitIMUL2_Reg_Imm, emitIMUL2_Reg_Reg_Quad, emitIMUL2_Reg_Reg, emitIMUL2_Reg_RegDisp_Quad, emitIMUL2_Reg_RegDisp, emitIMUL2_Reg_RegIdx_Quad, emitIMUL2_Reg_RegIdx, emitIMUL2_Reg_RegInd_Quad, emitIMUL2_Reg_RegInd, emitIMUL2_Reg_RegOff_Quad, emitIMUL2_Reg_RegOff, emitINC_Abs_Byte, emitINC_Abs_Quad, emitINC_Abs_Word, emitINC_Abs, emitINC_Reg_Byte, emitINC_Reg_Quad, emitINC_Reg_Word, emitINC_Reg, emitINC_RegDisp_Byte, emitINC_RegDisp_Quad, emitINC_RegDisp_Word, emitINC_RegDisp, emitINC_RegIdx_Byte, emitINC_RegIdx_Quad, emitINC_RegIdx_Word, emitINC_RegIdx, emitINC_RegInd_Byte, emitINC_RegInd_Quad, emitINC_RegInd_Word, emitINC_RegInd, emitINC_RegOff_Byte, emitINC_RegOff_Quad, emitINC_RegOff_Word, emitINC_RegOff, emitINT_Imm, emitJCC_Cond_Imm, emitJCC_Cond_ImmOrLabel, emitJCC_Cond_Label, emitJMP_Abs, emitJMP_Imm, emitJMP_ImmOrLabel, emitJMP_Label, emitJMP_Reg, emitJMP_RegDisp, emitJMP_RegIdx, emitJMP_RegInd, emitJMP_RegOff, emitLEA_Reg_Abs_Quad, emitLEA_Reg_Abs, emitLEA_Reg_RegDisp_Quad, emitLEA_Reg_RegDisp, emitLEA_Reg_RegIdx_Quad, emitLEA_Reg_RegIdx, emitLEA_Reg_RegInd_Quad, emitLEA_Reg_RegInd, emitLEA_Reg_RegOff_Quad, emitLEA_Reg_RegOff, emitLockNextInstruction, emitMETHODSTART_Reg, emitMFENCE, emitMOV_Abs_Imm_Byte, emitMOV_Abs_Imm_Quad, emitMOV_Abs_Imm_Word, emitMOV_Abs_Imm, emitMOV_Abs_Reg_Byte, emitMOV_Abs_Reg_Quad, emitMOV_Abs_Reg_Word, emitMOV_Abs_Reg, emitMOV_Reg_Abs_Byte, emitMOV_Reg_Abs_Quad, emitMOV_Reg_Abs_Word, emitMOV_Reg_Abs, emitMOV_Reg_Imm_Quad, emitMOV_Reg_Imm, emitMOV_Reg_Reg_Byte, emitMOV_Reg_Reg_Quad, emitMOV_Reg_Reg_Word, emitMOV_Reg_Reg, emitMOV_Reg_RegDisp_Byte, emitMOV_Reg_RegDisp_Quad, emitMOV_Reg_RegDisp_Word, emitMOV_Reg_RegDisp, emitMOV_Reg_RegIdx_Byte, emitMOV_Reg_RegIdx_Quad, emitMOV_Reg_RegIdx_Word, emitMOV_Reg_RegIdx, emitMOV_Reg_RegInd_Byte, emitMOV_Reg_RegInd_Quad, emitMOV_Reg_RegInd_Word, emitMOV_Reg_RegInd, emitMOV_Reg_RegOff_Byte, emitMOV_Reg_RegOff_Quad, emitMOV_Reg_RegOff_Word, emitMOV_Reg_RegOff, emitMOV_RegDisp_Imm_Byte, emitMOV_RegDisp_Imm_Quad, emitMOV_RegDisp_Imm_Word, emitMOV_RegDisp_Imm, emitMOV_RegDisp_Reg_Byte, emitMOV_RegDisp_Reg_Quad, emitMOV_RegDisp_Reg_Word, emitMOV_RegDisp_Reg, emitMOV_RegIdx_Imm_Byte, emitMOV_RegIdx_Imm_Quad, emitMOV_RegIdx_Imm_Word, emitMOV_RegIdx_Imm, emitMOV_RegIdx_Reg_Byte, emitMOV_RegIdx_Reg_Quad, emitMOV_RegIdx_Reg_Word, emitMOV_RegIdx_Reg, emitMOV_RegInd_Imm_Byte, emitMOV_RegInd_Imm_Quad, emitMOV_RegInd_Imm_Word, emitMOV_RegInd_Imm, emitMOV_RegInd_Reg_Byte, emitMOV_RegInd_Reg_Quad, emitMOV_RegInd_Reg_Word, emitMOV_RegInd_Reg, emitMOV_RegOff_Imm_Byte, emitMOV_RegOff_Imm_Quad, emitMOV_RegOff_Imm_Word, emitMOV_RegOff_Imm, emitMOV_RegOff_Reg_Byte, emitMOV_RegOff_Reg_Quad, emitMOV_RegOff_Reg_Word, emitMOV_RegOff_Reg, emitMOVAPD_Abs_Reg, emitMOVAPD_Reg_Abs, emitMOVAPD_Reg_Reg, emitMOVAPD_Reg_RegDisp, emitMOVAPD_Reg_RegIdx, emitMOVAPD_Reg_RegInd, emitMOVAPD_Reg_RegOff, emitMOVAPD_RegDisp_Reg, emitMOVAPD_RegIdx_Reg, emitMOVAPD_RegInd_Reg, emitMOVAPD_RegOff_Reg, emitMOVAPS_Abs_Reg, emitMOVAPS_Reg_Abs, emitMOVAPS_Reg_Reg, emitMOVAPS_Reg_RegDisp, emitMOVAPS_Reg_RegIdx, emitMOVAPS_Reg_RegInd, emitMOVAPS_Reg_RegOff, emitMOVAPS_RegDisp_Reg, emitMOVAPS_RegIdx_Reg, emitMOVAPS_RegInd_Reg, emitMOVAPS_RegOff_Reg, emitMOVD_Abs_Reg, emitMOVD_Abs_Reg, emitMOVD_Reg_Abs, emitMOVD_Reg_Abs, emitMOVD_Reg_Reg, emitMOVD_Reg_Reg, emitMOVD_Reg_Reg, emitMOVD_Reg_Reg, emitMOVD_Reg_RegDisp, emitMOVD_Reg_RegDisp, emitMOVD_Reg_RegIdx, emitMOVD_Reg_RegIdx, emitMOVD_Reg_RegInd, emitMOVD_Reg_RegInd, emitMOVD_Reg_RegOff, emitMOVD_Reg_RegOff, emitMOVD_RegDisp_Reg, emitMOVD_RegDisp_Reg, emitMOVD_RegIdx_Reg, emitMOVD_RegIdx_Reg, emitMOVD_RegInd_Reg, emitMOVD_RegInd_Reg, emitMOVD_RegOff_Reg, emitMOVD_RegOff_Reg, emitMOVLPD_Abs_Reg, emitMOVLPD_Reg_Abs, emitMOVLPD_Reg_Reg, emitMOVLPD_Reg_RegDisp, emitMOVLPD_Reg_RegIdx, emitMOVLPD_Reg_RegInd, emitMOVLPD_Reg_RegOff, emitMOVLPD_RegDisp_Reg, emitMOVLPD_RegIdx_Reg, emitMOVLPD_RegInd_Reg, emitMOVLPD_RegOff_Reg, emitMOVLPS_Abs_Reg, emitMOVLPS_Reg_Abs, emitMOVLPS_Reg_Reg, emitMOVLPS_Reg_RegDisp, emitMOVLPS_Reg_RegIdx, emitMOVLPS_Reg_RegInd, emitMOVLPS_Reg_RegOff, emitMOVLPS_RegDisp_Reg, emitMOVLPS_RegIdx_Reg, emitMOVLPS_RegInd_Reg, emitMOVLPS_RegOff_Reg, emitMOVQ_Abs_Reg, emitMOVQ_Abs_Reg, emitMOVQ_Reg_Abs, emitMOVQ_Reg_Abs, emitMOVQ_Reg_Reg, emitMOVQ_Reg_Reg, emitMOVQ_Reg_RegDisp, emitMOVQ_Reg_RegDisp, emitMOVQ_Reg_RegIdx, emitMOVQ_Reg_RegIdx, emitMOVQ_Reg_RegInd, emitMOVQ_Reg_RegInd, emitMOVQ_Reg_RegOff, emitMOVQ_Reg_RegOff, emitMOVQ_RegDisp_Reg, emitMOVQ_RegDisp_Reg, emitMOVQ_RegIdx_Reg, emitMOVQ_RegIdx_Reg, emitMOVQ_RegInd_Reg, emitMOVQ_RegInd_Reg, emitMOVQ_RegOff_Reg, emitMOVQ_RegOff_Reg, emitMOVSD_Abs_Reg, emitMOVSD_Reg_Abs, emitMOVSD_Reg_Reg, emitMOVSD_Reg_RegDisp, emitMOVSD_Reg_RegIdx, emitMOVSD_Reg_RegInd, emitMOVSD_Reg_RegOff, emitMOVSD_RegDisp_Reg, emitMOVSD_RegIdx_Reg, emitMOVSD_RegInd_Reg, emitMOVSD_RegOff_Reg, emitMOVSS_Abs_Reg, emitMOVSS_Reg_Abs, emitMOVSS_Reg_Reg, emitMOVSS_Reg_RegDisp, emitMOVSS_Reg_RegIdx, emitMOVSS_Reg_RegInd, emitMOVSS_Reg_RegOff, emitMOVSS_RegDisp_Reg, emitMOVSS_RegIdx_Reg, emitMOVSS_RegInd_Reg, emitMOVSS_RegOff_Reg, emitMOVSX_Reg_Abs_Byte, emitMOVSX_Reg_Abs_Word, emitMOVSX_Reg_Reg_Byte, emitMOVSX_Reg_Reg_Word, emitMOVSX_Reg_RegDisp_Byte, emitMOVSX_Reg_RegDisp_Word, emitMOVSX_Reg_RegIdx_Byte, emitMOVSX_Reg_RegIdx_Word, emitMOVSX_Reg_RegInd_Byte, emitMOVSX_Reg_RegInd_Word, emitMOVSX_Reg_RegOff_Byte, emitMOVSX_Reg_RegOff_Word, emitMOVSXDQ_Reg_Abs, emitMOVSXDQ_Reg_Reg, emitMOVSXDQ_Reg_RegDisp, emitMOVSXDQ_Reg_RegIdx, emitMOVSXDQ_Reg_RegInd, emitMOVSXDQ_Reg_RegOff, emitMOVSXQ_Reg_Abs_Byte, emitMOVSXQ_Reg_Abs_Word, emitMOVSXQ_Reg_Reg_Byte, emitMOVSXQ_Reg_Reg_Word, emitMOVSXQ_Reg_RegDisp_Byte, emitMOVSXQ_Reg_RegDisp_Word, emitMOVSXQ_Reg_RegIdx_Byte, emitMOVSXQ_Reg_RegIdx_Word, emitMOVSXQ_Reg_RegInd_Byte, emitMOVSXQ_Reg_RegInd_Word, emitMOVSXQ_Reg_RegOff_Byte, emitMOVSXQ_Reg_RegOff_Word, emitMOVZX_Reg_Abs_Byte, emitMOVZX_Reg_Abs_Word, emitMOVZX_Reg_Reg_Byte, emitMOVZX_Reg_Reg_Word, emitMOVZX_Reg_RegDisp_Byte, emitMOVZX_Reg_RegDisp_Word, emitMOVZX_Reg_RegIdx_Byte, emitMOVZX_Reg_RegIdx_Word, emitMOVZX_Reg_RegInd_Byte, emitMOVZX_Reg_RegInd_Word, emitMOVZX_Reg_RegOff_Byte, emitMOVZX_Reg_RegOff_Word, emitMOVZXQ_Reg_Abs_Byte, emitMOVZXQ_Reg_Abs_Word, emitMOVZXQ_Reg_Reg_Byte, emitMOVZXQ_Reg_Reg_Word, emitMOVZXQ_Reg_RegDisp_Byte, emitMOVZXQ_Reg_RegDisp_Word, emitMOVZXQ_Reg_RegIdx_Byte, emitMOVZXQ_Reg_RegIdx_Word, emitMOVZXQ_Reg_RegInd_Byte, emitMOVZXQ_Reg_RegInd_Word, emitMOVZXQ_Reg_RegOff_Byte, emitMOVZXQ_Reg_RegOff_Word, emitMUL_Reg_Abs_Quad, emitMUL_Reg_Abs, emitMUL_Reg_Reg_Quad, emitMUL_Reg_Reg, emitMUL_Reg_RegDisp_Quad, emitMUL_Reg_RegDisp, emitMUL_Reg_RegIdx_Quad, emitMUL_Reg_RegIdx, emitMUL_Reg_RegInd_Quad, emitMUL_Reg_RegInd, emitMUL_Reg_RegOff_Quad, emitMUL_Reg_RegOff, emitMULSD_Reg_Abs, emitMULSD_Reg_Reg, emitMULSD_Reg_RegDisp, emitMULSD_Reg_RegIdx, emitMULSD_Reg_RegInd, emitMULSD_Reg_RegOff, emitMULSS_Reg_Abs, emitMULSS_Reg_Reg, emitMULSS_Reg_RegDisp, emitMULSS_Reg_RegIdx, emitMULSS_Reg_RegInd, emitMULSS_Reg_RegOff, emitNEG_Abs_Byte, emitNEG_Abs_Quad, emitNEG_Abs_Word, emitNEG_Abs, emitNEG_Reg_Byte, emitNEG_Reg_Quad, emitNEG_Reg_Word, emitNEG_Reg, emitNEG_RegDisp_Byte, emitNEG_RegDisp_Quad, emitNEG_RegDisp_Word, emitNEG_RegDisp, emitNEG_RegIdx_Byte, emitNEG_RegIdx_Quad, emitNEG_RegIdx_Word, emitNEG_RegIdx, emitNEG_RegInd_Byte, emitNEG_RegInd_Quad, emitNEG_RegInd_Word, emitNEG_RegInd, emitNEG_RegOff_Byte, emitNEG_RegOff_Quad, emitNEG_RegOff_Word, emitNEG_RegOff, emitNOP, emitNOT_Abs_Byte, emitNOT_Abs_Quad, emitNOT_Abs_Word, emitNOT_Abs, emitNOT_Reg_Byte, emitNOT_Reg_Quad, emitNOT_Reg_Word, emitNOT_Reg, emitNOT_RegDisp_Byte, emitNOT_RegDisp_Quad, emitNOT_RegDisp_Word, emitNOT_RegDisp, emitNOT_RegIdx_Byte, emitNOT_RegIdx_Quad, emitNOT_RegIdx_Word, emitNOT_RegIdx, emitNOT_RegInd_Byte, emitNOT_RegInd_Quad, emitNOT_RegInd_Word, emitNOT_RegInd, emitNOT_RegOff_Byte, emitNOT_RegOff_Quad, emitNOT_RegOff_Word, emitNOT_RegOff, emitOFFSET_Imm_ImmOrLabel, emitOR_Abs_Imm_Byte, emitOR_Abs_Imm_Quad, emitOR_Abs_Imm_Word, emitOR_Abs_Imm, emitOR_Abs_Reg_Byte, emitOR_Abs_Reg_Quad, emitOR_Abs_Reg_Word, emitOR_Abs_Reg, emitOR_Reg_Abs_Byte, emitOR_Reg_Abs_Quad, emitOR_Reg_Abs_Word, emitOR_Reg_Abs, emitOR_Reg_Imm_Byte, emitOR_Reg_Imm_Quad, emitOR_Reg_Imm_Word, emitOR_Reg_Imm, emitOR_Reg_Reg_Byte, emitOR_Reg_Reg_Quad, emitOR_Reg_Reg_Word, emitOR_Reg_Reg, emitOR_Reg_RegDisp_Byte, emitOR_Reg_RegDisp_Quad, emitOR_Reg_RegDisp_Word, emitOR_Reg_RegDisp, emitOR_Reg_RegIdx_Byte, emitOR_Reg_RegIdx_Quad, emitOR_Reg_RegIdx_Word, emitOR_Reg_RegIdx, emitOR_Reg_RegInd_Byte, emitOR_Reg_RegInd_Quad, emitOR_Reg_RegInd_Word, emitOR_Reg_RegInd, emitOR_Reg_RegOff_Byte, emitOR_Reg_RegOff_Quad, emitOR_Reg_RegOff_Word, emitOR_Reg_RegOff, emitOR_RegDisp_Imm_Byte, emitOR_RegDisp_Imm_Quad, emitOR_RegDisp_Imm_Word, emitOR_RegDisp_Imm, emitOR_RegDisp_Reg_Byte, emitOR_RegDisp_Reg_Quad, emitOR_RegDisp_Reg_Word, emitOR_RegDisp_Reg, emitOR_RegIdx_Imm_Byte, emitOR_RegIdx_Imm_Quad, emitOR_RegIdx_Imm_Word, emitOR_RegIdx_Imm, emitOR_RegIdx_Reg_Byte, emitOR_RegIdx_Reg_Quad, emitOR_RegIdx_Reg_Word, emitOR_RegIdx_Reg, emitOR_RegInd_Imm_Byte, emitOR_RegInd_Imm_Quad, emitOR_RegInd_Imm_Word, emitOR_RegInd_Imm, emitOR_RegInd_Reg_Byte, emitOR_RegInd_Reg_Quad, emitOR_RegInd_Reg_Word, emitOR_RegInd_Reg, emitOR_RegOff_Imm_Byte, emitOR_RegOff_Imm_Quad, emitOR_RegOff_Imm_Word, emitOR_RegOff_Imm, emitOR_RegOff_Reg_Byte, emitOR_RegOff_Reg_Quad, emitOR_RegOff_Reg_Word, emitOR_RegOff_Reg, emitORPD_Reg_Abs, emitORPD_Reg_Reg, emitORPD_Reg_RegDisp, emitORPD_Reg_RegIdx, emitORPD_Reg_RegInd, emitORPD_Reg_RegOff, emitORPS_Reg_Abs, emitORPS_Reg_Reg, emitORPS_Reg_RegDisp, emitORPS_Reg_RegIdx, emitORPS_Reg_RegInd, emitORPS_Reg_RegOff, emitPatchPoint, emitPAUSE, emitPOP_Abs, emitPOP_Reg, emitPOP_RegDisp, emitPOP_RegIdx, emitPOP_RegInd, emitPOP_RegOff, emitPREFETCHNTA_Reg, emitPSLLQ_Reg_Abs, emitPSLLQ_Reg_Abs, emitPSLLQ_Reg_Reg, emitPSLLQ_Reg_Reg, emitPSLLQ_Reg_RegDisp, emitPSLLQ_Reg_RegDisp, emitPSLLQ_Reg_RegIdx, emitPSLLQ_Reg_RegIdx, emitPSLLQ_Reg_RegInd, emitPSLLQ_Reg_RegInd, emitPSLLQ_Reg_RegOff, emitPSLLQ_Reg_RegOff, emitPSRLQ_Reg_Abs, emitPSRLQ_Reg_Abs, emitPSRLQ_Reg_Reg, emitPSRLQ_Reg_Reg, emitPSRLQ_Reg_RegDisp, emitPSRLQ_Reg_RegDisp, emitPSRLQ_Reg_RegIdx, emitPSRLQ_Reg_RegIdx, emitPSRLQ_Reg_RegInd, emitPSRLQ_Reg_RegInd, emitPSRLQ_Reg_RegOff, emitPSRLQ_Reg_RegOff, emitPUSH_Abs, emitPUSH_Imm, emitPUSH_Reg, emitPUSH_RegDisp, emitPUSH_RegIdx, emitPUSH_RegInd, emitPUSH_RegOff, emitRCL_Abs_Imm_Byte, emitRCL_Abs_Imm_Quad, emitRCL_Abs_Imm_Word, emitRCL_Abs_Imm, emitRCL_Abs_Reg_Byte, emitRCL_Abs_Reg_Quad, emitRCL_Abs_Reg_Word, emitRCL_Abs_Reg, emitRCL_Reg_Imm_Byte, emitRCL_Reg_Imm_Quad, emitRCL_Reg_Imm_Word, emitRCL_Reg_Imm, emitRCL_Reg_Reg_Byte, emitRCL_Reg_Reg_Quad, emitRCL_Reg_Reg_Word, emitRCL_Reg_Reg, emitRCL_RegDisp_Imm_Byte, emitRCL_RegDisp_Imm_Quad, emitRCL_RegDisp_Imm_Word, emitRCL_RegDisp_Imm, emitRCL_RegDisp_Reg_Byte, emitRCL_RegDisp_Reg_Quad, emitRCL_RegDisp_Reg_Word, emitRCL_RegDisp_Reg, emitRCL_RegIdx_Imm_Byte, emitRCL_RegIdx_Imm_Quad, emitRCL_RegIdx_Imm_Word, emitRCL_RegIdx_Imm, emitRCL_RegIdx_Reg_Byte, emitRCL_RegIdx_Reg_Quad, emitRCL_RegIdx_Reg_Word, emitRCL_RegIdx_Reg, emitRCL_RegInd_Imm_Byte, emitRCL_RegInd_Imm_Quad, emitRCL_RegInd_Imm_Word, emitRCL_RegInd_Imm, emitRCL_RegInd_Reg_Byte, emitRCL_RegInd_Reg_Quad, emitRCL_RegInd_Reg_Word, emitRCL_RegInd_Reg, emitRCL_RegOff_Imm_Byte, emitRCL_RegOff_Imm_Quad, emitRCL_RegOff_Imm_Word, emitRCL_RegOff_Imm, emitRCL_RegOff_Reg_Byte, emitRCL_RegOff_Reg_Quad, emitRCL_RegOff_Reg_Word, emitRCL_RegOff_Reg, emitRCR_Abs_Imm_Byte, emitRCR_Abs_Imm_Quad, emitRCR_Abs_Imm_Word, emitRCR_Abs_Imm, emitRCR_Abs_Reg_Byte, emitRCR_Abs_Reg_Quad, emitRCR_Abs_Reg_Word, emitRCR_Abs_Reg, emitRCR_Reg_Imm_Byte, emitRCR_Reg_Imm_Quad, emitRCR_Reg_Imm_Word, emitRCR_Reg_Imm, emitRCR_Reg_Reg_Byte, emitRCR_Reg_Reg_Quad, emitRCR_Reg_Reg_Word, emitRCR_Reg_Reg, emitRCR_RegDisp_Imm_Byte, emitRCR_RegDisp_Imm_Quad, emitRCR_RegDisp_Imm_Word, emitRCR_RegDisp_Imm, emitRCR_RegDisp_Reg_Byte, emitRCR_RegDisp_Reg_Quad, emitRCR_RegDisp_Reg_Word, emitRCR_RegDisp_Reg, emitRCR_RegIdx_Imm_Byte, emitRCR_RegIdx_Imm_Quad, emitRCR_RegIdx_Imm_Word, emitRCR_RegIdx_Imm, emitRCR_RegIdx_Reg_Byte, emitRCR_RegIdx_Reg_Quad, emitRCR_RegIdx_Reg_Word, emitRCR_RegIdx_Reg, emitRCR_RegInd_Imm_Byte, emitRCR_RegInd_Imm_Quad, emitRCR_RegInd_Imm_Word, emitRCR_RegInd_Imm, emitRCR_RegInd_Reg_Byte, emitRCR_RegInd_Reg_Quad, emitRCR_RegInd_Reg_Word, emitRCR_RegInd_Reg, emitRCR_RegOff_Imm_Byte, emitRCR_RegOff_Imm_Quad, emitRCR_RegOff_Imm_Word, emitRCR_RegOff_Imm, emitRCR_RegOff_Reg_Byte, emitRCR_RegOff_Reg_Quad, emitRCR_RegOff_Reg_Word, emitRCR_RegOff_Reg, emitRDTSC, emitRET_Imm, emitRET, emitROL_Abs_Imm_Byte, emitROL_Abs_Imm_Quad, emitROL_Abs_Imm_Word, emitROL_Abs_Imm, emitROL_Abs_Reg_Byte, emitROL_Abs_Reg_Quad, emitROL_Abs_Reg_Word, emitROL_Abs_Reg, emitROL_Reg_Imm_Byte, emitROL_Reg_Imm_Quad, emitROL_Reg_Imm_Word, emitROL_Reg_Imm, emitROL_Reg_Reg_Byte, emitROL_Reg_Reg_Quad, emitROL_Reg_Reg_Word, emitROL_Reg_Reg, emitROL_RegDisp_Imm_Byte, emitROL_RegDisp_Imm_Quad, emitROL_RegDisp_Imm_Word, emitROL_RegDisp_Imm, emitROL_RegDisp_Reg_Byte, emitROL_RegDisp_Reg_Quad, emitROL_RegDisp_Reg_Word, emitROL_RegDisp_Reg, emitROL_RegIdx_Imm_Byte, emitROL_RegIdx_Imm_Quad, emitROL_RegIdx_Imm_Word, emitROL_RegIdx_Imm, emitROL_RegIdx_Reg_Byte, emitROL_RegIdx_Reg_Quad, emitROL_RegIdx_Reg_Word, emitROL_RegIdx_Reg, emitROL_RegInd_Imm_Byte, emitROL_RegInd_Imm_Quad, emitROL_RegInd_Imm_Word, emitROL_RegInd_Imm, emitROL_RegInd_Reg_Byte, emitROL_RegInd_Reg_Quad, emitROL_RegInd_Reg_Word, emitROL_RegInd_Reg, emitROL_RegOff_Imm_Byte, emitROL_RegOff_Imm_Quad, emitROL_RegOff_Imm_Word, emitROL_RegOff_Imm, emitROL_RegOff_Reg_Byte, emitROL_RegOff_Reg_Quad, emitROL_RegOff_Reg_Word, emitROL_RegOff_Reg, emitROR_Abs_Imm_Byte, emitROR_Abs_Imm_Quad, emitROR_Abs_Imm_Word, emitROR_Abs_Imm, emitROR_Abs_Reg_Byte, emitROR_Abs_Reg_Quad, emitROR_Abs_Reg_Word, emitROR_Abs_Reg, emitROR_Reg_Imm_Byte, emitROR_Reg_Imm_Quad, emitROR_Reg_Imm_Word, emitROR_Reg_Imm, emitROR_Reg_Reg_Byte, emitROR_Reg_Reg_Quad, emitROR_Reg_Reg_Word, emitROR_Reg_Reg, emitROR_RegDisp_Imm_Byte, emitROR_RegDisp_Imm_Quad, emitROR_RegDisp_Imm_Word, emitROR_RegDisp_Imm, emitROR_RegDisp_Reg_Byte, emitROR_RegDisp_Reg_Quad, emitROR_RegDisp_Reg_Word, emitROR_RegDisp_Reg, emitROR_RegIdx_Imm_Byte, emitROR_RegIdx_Imm_Quad, emitROR_RegIdx_Imm_Word, emitROR_RegIdx_Imm, emitROR_RegIdx_Reg_Byte, emitROR_RegIdx_Reg_Quad, emitROR_RegIdx_Reg_Word, emitROR_RegIdx_Reg, emitROR_RegInd_Imm_Byte, emitROR_RegInd_Imm_Quad, emitROR_RegInd_Imm_Word, emitROR_RegInd_Imm, emitROR_RegInd_Reg_Byte, emitROR_RegInd_Reg_Quad, emitROR_RegInd_Reg_Word, emitROR_RegInd_Reg, emitROR_RegOff_Imm_Byte, emitROR_RegOff_Imm_Quad, emitROR_RegOff_Imm_Word, emitROR_RegOff_Imm, emitROR_RegOff_Reg_Byte, emitROR_RegOff_Reg_Quad, emitROR_RegOff_Reg_Word, emitROR_RegOff_Reg, emitSAHF, emitSAL_Abs_Imm_Byte, emitSAL_Abs_Imm_Quad, emitSAL_Abs_Imm_Word, emitSAL_Abs_Imm, emitSAL_Abs_Reg_Byte, emitSAL_Abs_Reg_Quad, emitSAL_Abs_Reg_Word, emitSAL_Abs_Reg, emitSAL_Reg_Imm_Byte, emitSAL_Reg_Imm_Quad, emitSAL_Reg_Imm_Word, emitSAL_Reg_Imm, emitSAL_Reg_Reg_Byte, emitSAL_Reg_Reg_Quad, emitSAL_Reg_Reg_Word, emitSAL_Reg_Reg, emitSAL_RegDisp_Imm_Byte, emitSAL_RegDisp_Imm_Quad, emitSAL_RegDisp_Imm_Word, emitSAL_RegDisp_Imm, emitSAL_RegDisp_Reg_Byte, emitSAL_RegDisp_Reg_Quad, emitSAL_RegDisp_Reg_Word, emitSAL_RegDisp_Reg, emitSAL_RegIdx_Imm_Byte, emitSAL_RegIdx_Imm_Quad, emitSAL_RegIdx_Imm_Word, emitSAL_RegIdx_Imm, emitSAL_RegIdx_Reg_Byte, emitSAL_RegIdx_Reg_Quad, emitSAL_RegIdx_Reg_Word, emitSAL_RegIdx_Reg, emitSAL_RegInd_Imm_Byte, emitSAL_RegInd_Imm_Quad, emitSAL_RegInd_Imm_Word, emitSAL_RegInd_Imm, emitSAL_RegInd_Reg_Byte, emitSAL_RegInd_Reg_Quad, emitSAL_RegInd_Reg_Word, emitSAL_RegInd_Reg, emitSAL_RegOff_Imm_Byte, emitSAL_RegOff_Imm_Quad, emitSAL_RegOff_Imm_Word, emitSAL_RegOff_Imm, emitSAL_RegOff_Reg_Byte, emitSAL_RegOff_Reg_Quad, emitSAL_RegOff_Reg_Word, emitSAL_RegOff_Reg, emitSAR_Abs_Imm_Byte, emitSAR_Abs_Imm_Quad, emitSAR_Abs_Imm_Word, emitSAR_Abs_Imm, emitSAR_Abs_Reg_Byte, emitSAR_Abs_Reg_Quad, emitSAR_Abs_Reg_Word, emitSAR_Abs_Reg, emitSAR_Reg_Imm_Byte, emitSAR_Reg_Imm_Quad, emitSAR_Reg_Imm_Word, emitSAR_Reg_Imm, emitSAR_Reg_Reg_Byte, emitSAR_Reg_Reg_Quad, emitSAR_Reg_Reg_Word, emitSAR_Reg_Reg, emitSAR_RegDisp_Imm_Byte, emitSAR_RegDisp_Imm_Quad, emitSAR_RegDisp_Imm_Word, emitSAR_RegDisp_Imm, emitSAR_RegDisp_Reg_Byte, emitSAR_RegDisp_Reg_Quad, emitSAR_RegDisp_Reg_Word, emitSAR_RegDisp_Reg, emitSAR_RegIdx_Imm_Byte, emitSAR_RegIdx_Imm_Quad, emitSAR_RegIdx_Imm_Word, emitSAR_RegIdx_Imm, emitSAR_RegIdx_Reg_Byte, emitSAR_RegIdx_Reg_Quad, emitSAR_RegIdx_Reg_Word, emitSAR_RegIdx_Reg, emitSAR_RegInd_Imm_Byte, emitSAR_RegInd_Imm_Quad, emitSAR_RegInd_Imm_Word, emitSAR_RegInd_Imm, emitSAR_RegInd_Reg_Byte, emitSAR_RegInd_Reg_Quad, emitSAR_RegInd_Reg_Word, emitSAR_RegInd_Reg, emitSAR_RegOff_Imm_Byte, emitSAR_RegOff_Imm_Quad, emitSAR_RegOff_Imm_Word, emitSAR_RegOff_Imm, emitSAR_RegOff_Reg_Byte, emitSAR_RegOff_Reg_Quad, emitSAR_RegOff_Reg_Word, emitSAR_RegOff_Reg, emitSBB_Abs_Imm_Byte, emitSBB_Abs_Imm_Quad, emitSBB_Abs_Imm_Word, emitSBB_Abs_Imm, emitSBB_Abs_Reg_Byte, emitSBB_Abs_Reg_Quad, emitSBB_Abs_Reg_Word, emitSBB_Abs_Reg, emitSBB_Reg_Abs_Byte, emitSBB_Reg_Abs_Quad, emitSBB_Reg_Abs_Word, emitSBB_Reg_Abs, emitSBB_Reg_Imm_Byte, emitSBB_Reg_Imm_Quad, emitSBB_Reg_Imm_Word, emitSBB_Reg_Imm, emitSBB_Reg_Reg_Byte, emitSBB_Reg_Reg_Quad, emitSBB_Reg_Reg_Word, emitSBB_Reg_Reg, emitSBB_Reg_RegDisp_Byte, emitSBB_Reg_RegDisp_Quad, emitSBB_Reg_RegDisp_Word, emitSBB_Reg_RegDisp, emitSBB_Reg_RegIdx_Byte, emitSBB_Reg_RegIdx_Quad, emitSBB_Reg_RegIdx_Word, emitSBB_Reg_RegIdx, emitSBB_Reg_RegInd_Byte, emitSBB_Reg_RegInd_Quad, emitSBB_Reg_RegInd_Word, emitSBB_Reg_RegInd, emitSBB_Reg_RegOff_Byte, emitSBB_Reg_RegOff_Quad, emitSBB_Reg_RegOff_Word, emitSBB_Reg_RegOff, emitSBB_RegDisp_Imm_Byte, emitSBB_RegDisp_Imm_Quad, emitSBB_RegDisp_Imm_Word, emitSBB_RegDisp_Imm, emitSBB_RegDisp_Reg_Byte, emitSBB_RegDisp_Reg_Quad, emitSBB_RegDisp_Reg_Word, emitSBB_RegDisp_Reg, emitSBB_RegIdx_Imm_Byte, emitSBB_RegIdx_Imm_Quad, emitSBB_RegIdx_Imm_Word, emitSBB_RegIdx_Imm, emitSBB_RegIdx_Reg_Byte, emitSBB_RegIdx_Reg_Quad, emitSBB_RegIdx_Reg_Word, emitSBB_RegIdx_Reg, emitSBB_RegInd_Imm_Byte, emitSBB_RegInd_Imm_Quad, emitSBB_RegInd_Imm_Word, emitSBB_RegInd_Imm, emitSBB_RegInd_Reg_Byte, emitSBB_RegInd_Reg_Quad, emitSBB_RegInd_Reg_Word, emitSBB_RegInd_Reg, emitSBB_RegOff_Imm_Byte, emitSBB_RegOff_Imm_Quad, emitSBB_RegOff_Imm_Word, emitSBB_RegOff_Imm, emitSBB_RegOff_Reg_Byte, emitSBB_RegOff_Reg_Quad, emitSBB_RegOff_Reg_Word, emitSBB_RegOff_Reg, emitSET_Cond_Abs_Byte, emitSET_Cond_Reg_Byte, emitSET_Cond_RegDisp_Byte, emitSET_Cond_RegIdx_Byte, emitSET_Cond_RegInd_Byte, emitSET_Cond_RegOff_Byte, emitSHL_Abs_Imm_Byte, emitSHL_Abs_Imm_Quad, emitSHL_Abs_Imm_Word, emitSHL_Abs_Imm, emitSHL_Abs_Reg_Byte, emitSHL_Abs_Reg_Quad, emitSHL_Abs_Reg_Word, emitSHL_Abs_Reg, emitSHL_Reg_Imm_Byte, emitSHL_Reg_Imm_Quad, emitSHL_Reg_Imm_Word, emitSHL_Reg_Imm, emitSHL_Reg_Reg_Byte, emitSHL_Reg_Reg_Quad, emitSHL_Reg_Reg_Word, emitSHL_Reg_Reg, emitSHL_RegDisp_Imm_Byte, emitSHL_RegDisp_Imm_Quad, emitSHL_RegDisp_Imm_Word, emitSHL_RegDisp_Imm, emitSHL_RegDisp_Reg_Byte, emitSHL_RegDisp_Reg_Quad, emitSHL_RegDisp_Reg_Word, emitSHL_RegDisp_Reg, emitSHL_RegIdx_Imm_Byte, emitSHL_RegIdx_Imm_Quad, emitSHL_RegIdx_Imm_Word, emitSHL_RegIdx_Imm, emitSHL_RegIdx_Reg_Byte, emitSHL_RegIdx_Reg_Quad, emitSHL_RegIdx_Reg_Word, emitSHL_RegIdx_Reg, emitSHL_RegInd_Imm_Byte, emitSHL_RegInd_Imm_Quad, emitSHL_RegInd_Imm_Word, emitSHL_RegInd_Imm, emitSHL_RegInd_Reg_Byte, emitSHL_RegInd_Reg_Quad, emitSHL_RegInd_Reg_Word, emitSHL_RegInd_Reg, emitSHL_RegOff_Imm_Byte, emitSHL_RegOff_Imm_Quad, emitSHL_RegOff_Imm_Word, emitSHL_RegOff_Imm, emitSHL_RegOff_Reg_Byte, emitSHL_RegOff_Reg_Quad, emitSHL_RegOff_Reg_Word, emitSHL_RegOff_Reg, emitSHLD_Abs_Reg_Imm_Quad, emitSHLD_Abs_Reg_Imm, emitSHLD_Abs_Reg_Reg_Quad, emitSHLD_Abs_Reg_Reg, emitSHLD_Reg_Reg_Imm_Quad, emitSHLD_Reg_Reg_Imm, emitSHLD_Reg_Reg_Reg_Quad, emitSHLD_Reg_Reg_Reg, emitSHLD_RegDisp_Reg_Imm_Quad, emitSHLD_RegDisp_Reg_Imm, emitSHLD_RegDisp_Reg_Reg_Quad, emitSHLD_RegDisp_Reg_Reg, emitSHLD_RegIdx_Reg_Imm_Quad, emitSHLD_RegIdx_Reg_Imm, emitSHLD_RegIdx_Reg_Reg_Quad, emitSHLD_RegIdx_Reg_Reg, emitSHLD_RegInd_Reg_Imm_Quad, emitSHLD_RegInd_Reg_Imm, emitSHLD_RegInd_Reg_Reg_Quad, emitSHLD_RegInd_Reg_Reg, emitSHLD_RegOff_Reg_Imm_Quad, emitSHLD_RegOff_Reg_Imm, emitSHLD_RegOff_Reg_Reg_Quad, emitSHLD_RegOff_Reg_Reg, emitSHR_Abs_Imm_Byte, emitSHR_Abs_Imm_Quad, emitSHR_Abs_Imm_Word, emitSHR_Abs_Imm, emitSHR_Abs_Reg_Byte, emitSHR_Abs_Reg_Quad, emitSHR_Abs_Reg_Word, emitSHR_Abs_Reg, emitSHR_Reg_Imm_Byte, emitSHR_Reg_Imm_Quad, emitSHR_Reg_Imm_Word, emitSHR_Reg_Imm, emitSHR_Reg_Reg_Byte, emitSHR_Reg_Reg_Quad, emitSHR_Reg_Reg_Word, emitSHR_Reg_Reg, emitSHR_RegDisp_Imm_Byte, emitSHR_RegDisp_Imm_Quad, emitSHR_RegDisp_Imm_Word, emitSHR_RegDisp_Imm, emitSHR_RegDisp_Reg_Byte, emitSHR_RegDisp_Reg_Quad, emitSHR_RegDisp_Reg_Word, emitSHR_RegDisp_Reg, emitSHR_RegIdx_Imm_Byte, emitSHR_RegIdx_Imm_Quad, emitSHR_RegIdx_Imm_Word, emitSHR_RegIdx_Imm, emitSHR_RegIdx_Reg_Byte, emitSHR_RegIdx_Reg_Quad, emitSHR_RegIdx_Reg_Word, emitSHR_RegIdx_Reg, emitSHR_RegInd_Imm_Byte, emitSHR_RegInd_Imm_Quad, emitSHR_RegInd_Imm_Word, emitSHR_RegInd_Imm, emitSHR_RegInd_Reg_Byte, emitSHR_RegInd_Reg_Quad, emitSHR_RegInd_Reg_Word, emitSHR_RegInd_Reg, emitSHR_RegOff_Imm_Byte, emitSHR_RegOff_Imm_Quad, emitSHR_RegOff_Imm_Word, emitSHR_RegOff_Imm, emitSHR_RegOff_Reg_Byte, emitSHR_RegOff_Reg_Quad, emitSHR_RegOff_Reg_Word, emitSHR_RegOff_Reg, emitSHRD_Abs_Reg_Imm_Quad, emitSHRD_Abs_Reg_Imm, emitSHRD_Abs_Reg_Reg_Quad, emitSHRD_Abs_Reg_Reg, emitSHRD_Reg_Reg_Imm_Quad, emitSHRD_Reg_Reg_Imm, emitSHRD_Reg_Reg_Reg_Quad, emitSHRD_Reg_Reg_Reg, emitSHRD_RegDisp_Reg_Imm_Quad, emitSHRD_RegDisp_Reg_Imm, emitSHRD_RegDisp_Reg_Reg_Quad, emitSHRD_RegDisp_Reg_Reg, emitSHRD_RegIdx_Reg_Imm_Quad, emitSHRD_RegIdx_Reg_Imm, emitSHRD_RegIdx_Reg_Reg_Quad, emitSHRD_RegIdx_Reg_Reg, emitSHRD_RegInd_Reg_Imm_Quad, emitSHRD_RegInd_Reg_Imm, emitSHRD_RegInd_Reg_Reg_Quad, emitSHRD_RegInd_Reg_Reg, emitSHRD_RegOff_Reg_Imm_Quad, emitSHRD_RegOff_Reg_Imm, emitSHRD_RegOff_Reg_Reg_Quad, emitSHRD_RegOff_Reg_Reg, emitSQRTSD_Reg_Abs, emitSQRTSD_Reg_Reg, emitSQRTSD_Reg_RegDisp, emitSQRTSD_Reg_RegIdx, emitSQRTSD_Reg_RegInd, emitSQRTSD_Reg_RegOff, emitSQRTSS_Reg_Abs, emitSQRTSS_Reg_Reg, emitSQRTSS_Reg_RegDisp, emitSQRTSS_Reg_RegIdx, emitSQRTSS_Reg_RegInd, emitSQRTSS_Reg_RegOff, emitSUB_Abs_Imm_Byte, emitSUB_Abs_Imm_Quad, emitSUB_Abs_Imm_Word, emitSUB_Abs_Imm, emitSUB_Abs_Reg_Byte, emitSUB_Abs_Reg_Quad, emitSUB_Abs_Reg_Word, emitSUB_Abs_Reg, emitSUB_Reg_Abs_Byte, emitSUB_Reg_Abs_Quad, emitSUB_Reg_Abs_Word, emitSUB_Reg_Abs, emitSUB_Reg_Imm_Byte, emitSUB_Reg_Imm_Quad, emitSUB_Reg_Imm_Word, emitSUB_Reg_Imm, emitSUB_Reg_Reg_Byte, emitSUB_Reg_Reg_Quad, emitSUB_Reg_Reg_Word, emitSUB_Reg_Reg, emitSUB_Reg_RegDisp_Byte, emitSUB_Reg_RegDisp_Quad, emitSUB_Reg_RegDisp_Word, emitSUB_Reg_RegDisp, emitSUB_Reg_RegIdx_Byte, emitSUB_Reg_RegIdx_Quad, emitSUB_Reg_RegIdx_Word, emitSUB_Reg_RegIdx, emitSUB_Reg_RegInd_Byte, emitSUB_Reg_RegInd_Quad, emitSUB_Reg_RegInd_Word, emitSUB_Reg_RegInd, emitSUB_Reg_RegOff_Byte, emitSUB_Reg_RegOff_Quad, emitSUB_Reg_RegOff_Word, emitSUB_Reg_RegOff, emitSUB_RegDisp_Imm_Byte, emitSUB_RegDisp_Imm_Quad, emitSUB_RegDisp_Imm_Word, emitSUB_RegDisp_Imm, emitSUB_RegDisp_Reg_Byte, emitSUB_RegDisp_Reg_Quad, emitSUB_RegDisp_Reg_Word, emitSUB_RegDisp_Reg, emitSUB_RegIdx_Imm_Byte, emitSUB_RegIdx_Imm_Quad, emitSUB_RegIdx_Imm_Word, emitSUB_RegIdx_Imm, emitSUB_RegIdx_Reg_Byte, emitSUB_RegIdx_Reg_Quad, emitSUB_RegIdx_Reg_Word, emitSUB_RegIdx_Reg, emitSUB_RegInd_Imm_Byte, emitSUB_RegInd_Imm_Quad, emitSUB_RegInd_Imm_Word, emitSUB_RegInd_Imm, emitSUB_RegInd_Reg_Byte, emitSUB_RegInd_Reg_Quad, emitSUB_RegInd_Reg_Word, emitSUB_RegInd_Reg, emitSUB_RegOff_Imm_Byte, emitSUB_RegOff_Imm_Quad, emitSUB_RegOff_Imm_Word, emitSUB_RegOff_Imm, emitSUB_RegOff_Reg_Byte, emitSUB_RegOff_Reg_Quad, emitSUB_RegOff_Reg_Word, emitSUB_RegOff_Reg, emitSUBSD_Reg_Abs, emitSUBSD_Reg_Reg, emitSUBSD_Reg_RegDisp, emitSUBSD_Reg_RegIdx, emitSUBSD_Reg_RegInd, emitSUBSD_Reg_RegOff, emitSUBSS_Reg_Abs, emitSUBSS_Reg_Reg, emitSUBSS_Reg_RegDisp, emitSUBSS_Reg_RegIdx, emitSUBSS_Reg_RegInd, emitSUBSS_Reg_RegOff, emitTEST_Abs_Imm_Byte, emitTEST_Abs_Imm_Quad, emitTEST_Abs_Imm_Word, emitTEST_Abs_Imm, emitTEST_Abs_Reg_Byte, emitTEST_Abs_Reg_Quad, emitTEST_Abs_Reg_Word, emitTEST_Abs_Reg, emitTEST_Reg_Imm_Byte, emitTEST_Reg_Imm_Quad, emitTEST_Reg_Imm_Word, emitTEST_Reg_Imm, emitTEST_Reg_Reg_Byte, emitTEST_Reg_Reg_Quad, emitTEST_Reg_Reg_Word, emitTEST_Reg_Reg, emitTEST_RegDisp_Imm_Byte, emitTEST_RegDisp_Imm_Quad, emitTEST_RegDisp_Imm_Word, emitTEST_RegDisp_Imm, emitTEST_RegDisp_Reg_Byte, emitTEST_RegDisp_Reg_Quad, emitTEST_RegDisp_Reg_Word, emitTEST_RegDisp_Reg, emitTEST_RegIdx_Imm_Byte, emitTEST_RegIdx_Imm_Quad, emitTEST_RegIdx_Imm_Word, emitTEST_RegIdx_Imm, emitTEST_RegIdx_Reg_Byte, emitTEST_RegIdx_Reg_Quad, emitTEST_RegIdx_Reg_Word, emitTEST_RegIdx_Reg, emitTEST_RegInd_Imm_Byte, emitTEST_RegInd_Imm_Quad, emitTEST_RegInd_Imm_Word, emitTEST_RegInd_Imm, emitTEST_RegInd_Reg_Byte, emitTEST_RegInd_Reg_Quad, emitTEST_RegInd_Reg_Word, emitTEST_RegInd_Reg, emitTEST_RegOff_Imm_Byte, emitTEST_RegOff_Imm_Quad, emitTEST_RegOff_Imm_Word, emitTEST_RegOff_Imm, emitTEST_RegOff_Reg_Byte, emitTEST_RegOff_Reg_Quad, emitTEST_RegOff_Reg_Word, emitTEST_RegOff_Reg, emitUCOMISD_Reg_Abs, emitUCOMISD_Reg_Reg, emitUCOMISD_Reg_RegDisp, emitUCOMISD_Reg_RegIdx, emitUCOMISD_Reg_RegInd, emitUCOMISD_Reg_RegOff, emitUCOMISS_Reg_Abs, emitUCOMISS_Reg_Reg, emitUCOMISS_Reg_RegDisp, emitUCOMISS_Reg_RegIdx, emitUCOMISS_Reg_RegInd, emitUCOMISS_Reg_RegOff, emitXOR_Abs_Imm_Byte, emitXOR_Abs_Imm_Quad, emitXOR_Abs_Imm_Word, emitXOR_Abs_Imm, emitXOR_Abs_Reg_Byte, emitXOR_Abs_Reg_Quad, emitXOR_Abs_Reg_Word, emitXOR_Abs_Reg, emitXOR_Reg_Abs_Byte, emitXOR_Reg_Abs_Quad, emitXOR_Reg_Abs_Word, emitXOR_Reg_Abs, emitXOR_Reg_Imm_Byte, emitXOR_Reg_Imm_Quad, emitXOR_Reg_Imm_Word, emitXOR_Reg_Imm, emitXOR_Reg_Reg_Byte, emitXOR_Reg_Reg_Quad, emitXOR_Reg_Reg_Word, emitXOR_Reg_Reg, emitXOR_Reg_RegDisp_Byte, emitXOR_Reg_RegDisp_Quad, emitXOR_Reg_RegDisp_Word, emitXOR_Reg_RegDisp, emitXOR_Reg_RegIdx_Byte, emitXOR_Reg_RegIdx_Quad, emitXOR_Reg_RegIdx_Word, emitXOR_Reg_RegIdx, emitXOR_Reg_RegInd_Byte, emitXOR_Reg_RegInd_Quad, emitXOR_Reg_RegInd_Word, emitXOR_Reg_RegInd, emitXOR_Reg_RegOff_Byte, emitXOR_Reg_RegOff_Quad, emitXOR_Reg_RegOff_Word, emitXOR_Reg_RegOff, emitXOR_RegDisp_Imm_Byte, emitXOR_RegDisp_Imm_Quad, emitXOR_RegDisp_Imm_Word, emitXOR_RegDisp_Imm, emitXOR_RegDisp_Reg_Byte, emitXOR_RegDisp_Reg_Quad, emitXOR_RegDisp_Reg_Word, emitXOR_RegDisp_Reg, emitXOR_RegIdx_Imm_Byte, emitXOR_RegIdx_Imm_Quad, emitXOR_RegIdx_Imm_Word, emitXOR_RegIdx_Imm, emitXOR_RegIdx_Reg_Byte, emitXOR_RegIdx_Reg_Quad, emitXOR_RegIdx_Reg_Word, emitXOR_RegIdx_Reg, emitXOR_RegInd_Imm_Byte, emitXOR_RegInd_Imm_Quad, emitXOR_RegInd_Imm_Word, emitXOR_RegInd_Imm, emitXOR_RegInd_Reg_Byte, emitXOR_RegInd_Reg_Quad, emitXOR_RegInd_Reg_Word, emitXOR_RegInd_Reg, emitXOR_RegOff_Imm_Byte, emitXOR_RegOff_Imm_Quad, emitXOR_RegOff_Imm_Word, emitXOR_RegOff_Imm, emitXOR_RegOff_Reg_Byte, emitXOR_RegOff_Reg_Quad, emitXOR_RegOff_Reg_Word, emitXOR_RegOff_Reg, emitXORPD_Reg_Abs, emitXORPD_Reg_Reg, emitXORPD_Reg_RegDisp, emitXORPD_Reg_RegIdx, emitXORPD_Reg_RegInd, emitXORPD_Reg_RegOff, emitXORPS_Reg_Abs, emitXORPS_Reg_Reg, emitXORPS_Reg_RegDisp, emitXORPS_Reg_RegIdx, emitXORPS_Reg_RegInd, emitXORPS_Reg_RegOff, flipCode, forwardJcc, forwardJECXZ, forwardJMP, generateJTOCcall, generateJTOCcall, generateJTOCcmpDouble, generateJTOCcmpFloat, generateJTOCcmpWord, generateJTOCjmp, generateJTOCloadInt, generateJTOCloadInt, generateJTOCloadLong, generateJTOCpop, generateJTOCpop, generateJTOCpush, generateJTOCpush, generateJTOCstoreInt, generateJTOCstoreInt, generateJTOCstoreLong, generateLoadReturnAddress, generatePendingJMP, getMachineCodeIndex, getMachineCodes, noteBytecode, patchCode, patchConditionalBranch, patchLoadReturnAddress, patchShortBranch, patchSwitchCase, patchSwitchTableDisplacement, patchUnconditionalBranch, resolveForwardReferences, setMachineCodes, writeLastInstruction

Methods inherited from class org.jikesrvm.compilers.common.assembler.AbstractAssembler
noteBranchBytecode, noteBytecode, noteBytecode, noteBytecode, noteBytecode, noteLookupswitchBytecode, noteTableswitchBytecode

Methods inherited from class java.lang.Object
clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait

- Field Detail
  - instructionCount
```
private int instructionCount
```
    The number of instructions emitted so far
- Constructor Detail
  - AssemblerOpt
```
public AssemblerOpt(int bcSize,
                    boolean print,
                    IR ir)
```
    Parameters:
    
    bcSize - initial machine code buffer size.
    
    print - whether to dump generated machine code.
    
    ir - the IR object for the opt compilation.
    
    See Also:
    
    Assembler
- Method Detail
  - doORPS
```
private void doORPS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ORPS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCVTSD2SIQ
```
private void doCVTSD2SIQ(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSD2SIQ operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCVTSI2SS
```
private void doCVTSI2SS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSI2SS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFUCOMIP
```
private void doFUCOMIP(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Compare instruction and has a FUCOMIP operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPEQSD
```
private void doCMPEQSD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPEQSD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCDO
```
private void doCDO(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_ConvertDW2QW instruction and has a CDO operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCDQ
```
private void doCDQ(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_ConvertDW2QW instruction and has a CDQ operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCVTTSD2SIQ
```
private void doCVTTSD2SIQ(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTTSD2SIQ operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doADDSS
```
private void doADDSS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ADDSS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFUCOMI
```
private void doFUCOMI(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Compare instruction and has a FUCOMI operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doBSWAP
```
private void doBSWAP(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a BSWAP operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPEQSS
```
private void doCMPEQSS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPEQSS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCVTSI2SD
```
private void doCVTSI2SD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSI2SD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doSUB
```
private void doSUB(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SUB operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doADDSD
```
private void doADDSD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ADDSD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFIADD
```
private void doFIADD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FIADD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFST
```
private void doFST(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a FST operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMP
```
private void doCMP(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Compare instruction and has a CMP operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMOVSD
```
private void doMOVSD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVSD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFSTP
```
private void doFSTP(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a FSTP operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCDQE
```
private void doCDQE(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_ConvertDW2QW instruction and has a CDQE operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMOVLPD
```
private void doMOVLPD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVLPD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMETHODSTART
```
private void doMETHODSTART(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a METHODSTART operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doBTC
```
private void doBTC(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Test instruction and has a BTC operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doPOP
```
private void doPOP(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a POP operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFLDLN2
```
private void doFLDLN2(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDLN2 operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doORPD
```
private void doORPD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ORPD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFIDIV
```
private void doFIDIV(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FIDIV operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPUNORDSS
```
private void doCMPUNORDSS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPUNORDSS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMOVSS
```
private void doMOVSS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVSS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFNINIT
```
private void doFNINIT(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Empty instruction and has a FNINIT operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doSUBSS
```
private void doSUBSS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SUBSS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCVTSD2SI
```
private void doCVTSD2SI(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSD2SI operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doXOR
```
private void doXOR(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a XOR operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doRCL
```
private void doRCL(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a RCL operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMOVSX
```
private void doMOVSX(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a MOVSX operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFSUB
```
private void doFSUB(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FSUB operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMOVLPS
```
private void doMOVLPS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVLPS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFLD
```
private void doFLD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a FLD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doPUSH
```
private void doPUSH(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_UnaryNoRes instruction and has a PUSH operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPLTSS
```
private void doCMPLTSS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPLTSS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doBTS
```
private void doBTS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Test instruction and has a BTS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doRCR
```
private void doRCR(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a RCR operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doBTR
```
private void doBTR(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Test instruction and has a BTR operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCALL
```
private void doCALL(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Call instruction and has a CALL operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doANDPS
```
private void doANDPS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ANDPS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doSET
```
private void doSET(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Set instruction and has a SET operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFIST
```
private void doFIST(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a FIST operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFFREE
```
private void doFFREE(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FFREE operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFLDPI
```
private void doFLDPI(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDPI operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPORDSS
```
private void doCMPORDSS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPORDSS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFDIV
```
private void doFDIV(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FDIV operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPNESS
```
private void doCMPNESS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNESS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doSQRTSD
```
private void doSQRTSD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a SQRTSD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doPAUSE
```
private void doPAUSE(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Empty instruction and has a PAUSE operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMOVZX
```
private void doMOVZX(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a MOVZX operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doBT
```
private void doBT(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Test instruction and has a BT operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCVTSS2SI
```
private void doCVTSS2SI(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSS2SI operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPNLESD
```
private void doCMPNLESD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNLESD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doANDPD
```
private void doANDPD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ANDPD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMOVSXDQ
```
private void doMOVSXDQ(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a MOVSXDQ operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCVTSS2SD
```
private void doCVTSS2SD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSS2SD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doOFFSET
```
private void doOFFSET(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_CaseLabel instruction and has a OFFSET operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFADD
```
private void doFADD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FADD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFILD
```
private void doFILD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a FILD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPNESD
```
private void doCMPNESD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNESD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCVTSI2SDQ
```
private void doCVTSI2SDQ(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSI2SDQ operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPORDSD
```
private void doCMPORDSD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPORDSD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMULSS
```
private void doMULSS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a MULSS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doPSLLQ
```
private void doPSLLQ(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a PSLLQ operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doSHRD
```
private void doSHRD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_DoubleShift instruction and has a SHRD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doDIVSD
```
private void doDIVSD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a DIVSD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFLDL2E
```
private void doFLDL2E(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDL2E operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPXCHG
```
private void doCMPXCHG(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_CompareExchange instruction and has a CMPXCHG operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMOVAPD
```
private void doMOVAPD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVAPD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFPREM
```
private void doFPREM(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FPREM operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doDIV
```
private void doDIV(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Divide instruction and has a DIV operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doNEG
```
private void doNEG(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a NEG operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doDIVSS
```
private void doDIVSS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a DIVSS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFLDL2T
```
private void doFLDL2T(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDL2T operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMOVAPS
```
private void doMOVAPS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVAPS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFSUBP
```
private void doFSUBP(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FSUBP operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFSUBR
```
private void doFSUBR(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FSUBR operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCVTTSS2SI
```
private void doCVTTSS2SI(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTTSS2SI operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doRET
```
private void doRET(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Return instruction and has a RET operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doADC
```
private void doADC(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ADC operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doADD
```
private void doADD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ADD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPLESD
```
private void doCMPLESD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPLESD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFISUB
```
private void doFISUB(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FISUB operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doXORPS
```
private void doXORPS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a XORPS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMFENCE
```
private void doMFENCE(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Empty instruction and has a MFENCE operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFCOMIP
```
private void doFCOMIP(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Compare instruction and has a FCOMIP operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFMULP
```
private void doFMULP(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FMULP operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPLESS
```
private void doCMPLESS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPLESS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFISTP
```
private void doFISTP(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a FISTP operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doRDTSC
```
private void doRDTSC(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_RDTSC instruction and has a RDTSC operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMULSD
```
private void doMULSD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a MULSD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doXORPD
```
private void doXORPD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a XORPD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFLD1
```
private void doFLD1(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLD1 operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFXCH
```
private void doFXCH(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_XChng instruction and has a FXCH operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doSHL
```
private void doSHL(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SHL operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doSHR
```
private void doSHR(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SHR operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPNLESS
```
private void doCMPNLESS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNLESS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFNSAVE
```
private void doFNSAVE(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_FSave instruction and has a FNSAVE operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMUL
```
private void doMUL(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Multiply instruction and has a MUL operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFCHS
```
private void doFCHS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a FCHS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFINIT
```
private void doFINIT(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Empty instruction and has a FINIT operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doIDIV
```
private void doIDIV(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Divide instruction and has a IDIV operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doSHLD
```
private void doSHLD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_DoubleShift instruction and has a SHLD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFFREEP
```
private void doFFREEP(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FFREEP operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doUCOMISD
```
private void doUCOMISD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Compare instruction and has a UCOMISD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doROL
```
private void doROL(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ROL operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doNOT
```
private void doNOT(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a NOT operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doROR
```
private void doROR(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ROR operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFCOMI
```
private void doFCOMI(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Compare instruction and has a FCOMI operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doTEST
```
private void doTEST(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Test instruction and has a TEST operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doAND
```
private void doAND(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a AND operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFNSTCW
```
private void doFNSTCW(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_UnaryNoRes instruction and has a FNSTCW operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMOVZXQ
```
private void doMOVZXQ(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a MOVZXQ operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFDIVRP
```
private void doFDIVRP(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FDIVRP operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFDIVR
```
private void doFDIVR(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FDIVR operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doSQRTSS
```
private void doSQRTSS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a SQRTSS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doUCOMISS
```
private void doUCOMISS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Compare instruction and has a UCOMISS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFMUL
```
private void doFMUL(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FMUL operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doINC
```
private void doINC(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a INC operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doSAL
```
private void doSAL(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SAL operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFDIVP
```
private void doFDIVP(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FDIVP operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPUNORDSD
```
private void doCMPUNORDSD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPUNORDSD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doSAR
```
private void doSAR(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SAR operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPXCHG8B
```
private void doCMPXCHG8B(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_CompareExchange8B instruction and has a CMPXCHG8B operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doSUBSD
```
private void doSUBSD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SUBSD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFSTSW
```
private void doFSTSW(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a FSTSW operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFADDP
```
private void doFADDP(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FADDP operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFLDCW
```
private void doFLDCW(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_UnaryNoRes instruction and has a FLDCW operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFRSTOR
```
private void doFRSTOR(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_FSave instruction and has a FRSTOR operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMOV
```
private void doCMOV(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_CondMove instruction and has a CMOV operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doINT
```
private void doINT(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Trap instruction and has a INT operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPLTSD
```
private void doCMPLTSD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPLTSD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCVTSD2SS
```
private void doCVTSD2SS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSD2SS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doSBB
```
private void doSBB(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SBB operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFIDIVR
```
private void doFIDIVR(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FIDIVR operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFSTCW
```
private void doFSTCW(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_UnaryNoRes instruction and has a FSTCW operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFLDLG2
```
private void doFLDLG2(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDLG2 operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doPREFETCHNTA
```
private void doPREFETCHNTA(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_CacheOp instruction and has a PREFETCHNTA operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPNLTSD
```
private void doCMPNLTSD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNLTSD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doOR
```
private void doOR(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a OR operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doDEC
```
private void doDEC(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a DEC operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCVTTSD2SI
```
private void doCVTTSD2SI(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTTSD2SI operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doLEA
```
private void doLEA(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Lea instruction and has a LEA operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFISUBR
```
private void doFISUBR(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FISUBR operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doANDNPS
```
private void doANDNPS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ANDNPS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFCMOV
```
private void doFCMOV(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_CondMove instruction and has a FCMOV operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doCMPNLTSS
```
private void doCMPNLTSS(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNLTSS operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMOVD
```
private void doMOVD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFSUBRP
```
private void doFSUBRP(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FSUBRP operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMOV
```
private void doMOV(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOV operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMOVQ
```
private void doMOVQ(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVQ operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doPSRLQ
```
private void doPSRLQ(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a PSRLQ operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFLDZ
```
private void doFLDZ(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDZ operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doANDNPD
```
private void doANDNPD(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ANDNPD operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doFIMUL
```
private void doFIMUL(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FIMUL operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doIMUL1
```
private void doIMUL1(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Multiply instruction and has a IMUL1 operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doMOVSXQ
```
private void doMOVSXQ(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_Unary instruction and has a MOVSXQ operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doIMUL2
```
private void doIMUL2(Instruction inst)
```
    Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a IMUL2 operator
    
    Parameters:
    
    inst - the instruction to assemble
  - doInst
```
public void doInst(Instruction inst)
```
    Description copied from class: AssemblerBase
    
    Assembles the given instruction.
    
    Specified by:
    
    doInst in class AssemblerBase
    
    Parameters:
    
    inst - the instruction to assemble

Class AssemblerOpt

Field Summary

Fields inherited from class org.jikesrvm.compilers.opt.mir2mc.ia32.AssemblerBase

Fields inherited from class org.jikesrvm.compilers.common.assembler.ia32.Assembler

Constructor Summary

Method Summary

Methods inherited from class org.jikesrvm.compilers.opt.mir2mc.ia32.AssemblerBase

Methods inherited from class org.jikesrvm.compilers.common.assembler.ia32.Assembler

Methods inherited from class org.jikesrvm.compilers.common.assembler.AbstractAssembler

Methods inherited from class java.lang.Object

Field Detail

instructionCount

Constructor Detail

AssemblerOpt

Method Detail

doORPS

doCVTSD2SIQ

doCVTSI2SS

doFUCOMIP

doCMPEQSD

doCDO

doCDQ

doCVTTSD2SIQ

doADDSS

doFUCOMI

doBSWAP

doCMPEQSS

doCVTSI2SD

doSUB

doADDSD

doFIADD

doFST

doCMP

doMOVSD

doFSTP

doCDQE

doMOVLPD

doMETHODSTART

doBTC

doPOP

doFLDLN2

doORPD

doFIDIV

doCMPUNORDSS

doMOVSS

doFNINIT

doSUBSS

doCVTSD2SI

doXOR

doRCL

doMOVSX

doFSUB

doMOVLPS

doFLD

doPUSH

doCMPLTSS

doBTS

doRCR

doBTR

doCALL

doANDPS

doSET

doFIST

doFFREE

doFLDPI

doCMPORDSS

doFDIV

doCMPNESS

doSQRTSD

doPAUSE

doMOVZX

doBT

doCVTSS2SI

doCMPNLESD

doANDPD

doMOVSXDQ

doCVTSS2SD

doOFFSET

doFADD

doFILD